Reconstituted wafer stack packaging with after-applied pad extensions

• US 8,883,562 B2
• Filed: 06/06/2013
• Issued: 11/11/2014
• Est. Priority Date: 07/27/2007
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Humpston, Giles, Ovrutsky, David, Mirkarimi, Laura Wills
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US13/911,555
• Publication Number:
  US 20130344652A1
• Time in Patent Office: 523 Days
• Field of Search: 257/E21.499, 257/E23.169, 257/E23.019, 257/E23.142, 257/E23.178, 257/E23.085, 257/94, 257/95, 257/99, 257/103, 257/685, 257/686, 257/758, 257/773, 257/777, 257/781, 257/786, 438/107, 438/109, 438/110, 438/113, 438/462
• US Class Current: 438/110
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

A stacked microelectronic unit is provided which can include a plurality of vertically stacked microelectronic elements each having a front surface, contacts exposed at the front surface, a rear surface and edges extending between the front and rear surfaces. Traces connected with the contacts may extend along the front surfaces towards edges of the microelectronic elements with the rear surface of at least one of the stacked microelectronic elements being adjacent to a top face of the microelectronic unit. A plurality of conductors may extend along edges of the microelectronic elements from the traces to the top face. The conductors may be conductively connected with unit contacts such that the unit contacts overlie the rear surface of the at least one microelectronic element adjacent to the top face.

Claims

1. A method of fabricating first and second stacked microelectronic units, comprising:

a) stacking and joining a plurality of microelectronic elements to form a stacked assembly thereof, each of the microelectronic elements having a front face, a rear face remote from the front face, contacts exposed at the front face, edges extending between the front and rear faces and traces connected to the contacts extending along the front face towards the edges, the front faces of at least some of the microelectronic elements overlying and confronting the rear faces of other microelectronic elements, wherein at least first and second microelectronic elements of the stacked assembly are spaced apart from one another in a direction parallel to their front faces, a third microelectronic element overlies the rear face of the first microelectronic element, and a fourth microelectronic element overlies the rear face of the second microelectronic element;

b) then forming at least one conductor extending from a trace of each of the first, second, third, and fourth microelectronic elements; and

c) severing the stacked assembly into the first and second microelectronic units, the first and second microelectronic units including the first and second microelectronic elements, respectively, such that a first portion of the at least one conductor extends along the edges of each of the first and third microelectronic elements and a second portion of the at least one conductor extends along the edges of each of the second and fourth microelectronic elements.

2. The method of claim 1, wherein each of the plurality of microelectronic elements is included in a microelectronic subassembly containing a plurality of microelectronic elements arranged in an array, wherein (a) includes stacking and joining a plurality of the microelectronic subassemblies and forming a plurality of openings extending between edges of stacked microelectronic elements therein.

3. The method of claim 1, wherein the plurality of microelectronic elements are stacked and joined to form a stacked assembly thereof on a carrier layer, and wherein the stacked assembly is severed into the first and second microelectronic units such that the carrier layer remains unsevered.

4. The method of claim 1, wherein alignment features are provided on the front faces of and adjacent to the edges of at least one of the first and second microelectronic elements, the method further comprising aligning edges of each of the microelectronic elements within the first and second stacked subassemblies using the alignment features.

5. The method of claim 4, further comprising forming the alignment features during and by the same processing as the traces on the front faces of the first and second microelectronic elements.

6. The method of claim 5, wherein at least some of the alignment features extend from the traces formed on the front faces of the first and second microelectronic elements.

7. The method of claim 4, wherein at least some of the alignment features include a material which is not included in the traces.

8. The method of claim 1, wherein at least one of a width and a length of the front faces of the first and third microelectronic elements differ.

9. The method of claim 1, wherein at least some of the conductors extend to unit contacts overlying and adjacent to the rear faces of the third and fourth microelectronic elements.

10. The method of claim 7, wherein solder balls are formed at the end of the at least one conductor to form the unit contacts.

11. The method of claim 1, further comprising exposing only a portion of a trace of at least one of the first and second stacked microelectronic units to form a unit contact for external interconnection thereof.

12. The method of claim 1, further comprising forming an inclined wall through the microelectronic elements of the first and third microelectronic elements, the inclined wall being at an angle relative to a normal direction with respect to a plane defined by the front faces of one of the first and second microelectronic elements and defining the edges of the microelectronic elements of the first and third microelectronic elements.

13. The method of claim 12, wherein the stacked assembly is formed on a carrier layer, and wherein the inclined wall does not extend through the carrier layer.

14. The method of claim 1, further comprising forming an overmold layer over the edges of at least the first and second microelectronic elements, the at least one conductor extending along the overmold layer.

15. The method of claim 1, wherein the first and second microelectronic elements are portions of a reconstituted wafer.

16. A stacked microelectronic unit, comprising:

first and second vertically stacked microelectronic elements, each of the first and second microelectronic elements having a front face, a rear face remote from the front face, edges extending between the front and rear faces, contacts at their respective front faces, each of the first and second microelectronic elements being electrically connectable and testable through the respective contacts;

a dielectric layer overlying at least first edges of the edges of the first and second microelectronic elements; and

conductive vias, each of the vias extending through one of a plurality of openings spaced apart within the dielectric layer and along the first edges of the first and second microelectronic elements, the vias being connected to traces at front faces of the microelectronic elements.

17. The stacked microelectronic unit of claim 16, wherein at least the first edge of the second microelectronic element overlies the first edge of the first microelectronic element.

18. A stacked microelectronic unit, comprising:

first and second vertically stacked microelectronic elements, wherein a front face of the first microelectronic element overlies at least one of a front face and a rear face of the second microelectronic element and at least one of a width and a length of the front faces of the first and second microelectronic elements differ;

a dielectric layer overlying edges of the first and second microelectronic elements;

a plurality of openings spaced apart within the dielectric layer in a lateral direction and extending along the first edges of the first and second microelectronic elements; and

leads extending through at least some of the plurality of openings, the leads being connected to traces at front faces of the microelectronic elements and extending along a first edge of the stacked unit.