Trench metal oxide semiconductor with recessed trench material and remote contacts

• US 8,883,580 B2
• Filed: 12/27/2012
• Issued: 11/11/2014
• Est. Priority Date: 04/19/2007
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pattanayak, Deva N., Terrill, Kyle, Shi, Sharon, Lee, Misha, Bai, Yuming, Lui, Kam, Chen, Kuo-in
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US13/728,997
• Publication Number:
  US 20140235023A1
• Time in Patent Office: 684 Days
• Field of Search: 257/54, 257/73, 257/260, 257/280, 257/449, 438/167, 438/570
• US Class Current: 438/167
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.

Claims

1. A method of fabricating a semiconductor device comprising a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, said method comprising:

forming a plurality of first trenches separated by mesas, said first trenches having sidewalls of a first height;

depositing conductive material within said first trenches to a height that is less than said first height;

forming a layer of insulating material over said conductive material;

forming a source metal layer over a first region that encompasses said first trenches and said mesas, wherein within said first region, said source metal layer is separated from said conductive material by said insulating material; and

forming a first electrical contact between said source metal layer and said conductive material in said first trenches, wherein said first electrical contact is outside of said first region.

2. The method of claim 1 wherein said insulating material comprises a gate oxide, said substrate comprises a p-type silicon substrate, said conductive material comprises polysilicon, and said source metal layer comprises a material selected from the group consisting of:

titanium nitride, titanium, and aluminum.

3. The method of claim 1 wherein said semiconductor device further comprises a metal oxide semiconductor field electrical transistor (MOSFET) formed on said substrate, said MOSFET and said TMBS in combination comprising a monolithically integrated structure.

4. The method of claim 3 further comprising:

forming a plurality of second trenches within said substrate, wherein said conductive material is also deposited within said second trenches;

forming p-body implants between said second trenches, wherein said source metal layer is disposed over a second region comprising said second trenches and said p-body implants;

forming source implants adjacent to each of said second trenches but separated from said conductive material in said second trenches by said insulating material; and

forming a second electrical contact between said conductive material in said second trenches and a gate metal, wherein said second electrical contact is outside of said second region.

5. The method of claim 1 further comprising, prior to said forming of said source metal layer:

forming a dielectric layer over said mesas and said first trenches;

etching away portions of said dielectric layer and exposing said mesas so that said source metal layer is in contact with said mesas when said source metal layer is subsequently formed, wherein said insulating material remains over said conductive material after said etching is performed.

6. The method of claim 5 wherein said dielectric layer comprises a dielectric stack comprising a layer of tetraethylorthosilicate (TEOS) and a layer of borophosphosilicate glass (BPSG).