Method for decomposing lines of an electronic circuit

• US 8,883,625 B2
• Filed: 03/21/2012
• Issued: 11/11/2014
• Est. Priority Date: 03/24/2011
• Status: Expired due to Fees

• Current Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV)
• Inventors: Farys, Vincent, Serret, Emmanuelle
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US13/425,759
• Publication Number:
  US 20120241975A1
• Time in Patent Office: 965 Days
• Field of Search: 438/129, 438/599, 438/671
• US Class Current: 438/599
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for defining parallel lines extending along a first direction in a same level of an integrated circuit, among which at least first and second lines separated by an even number of lines are interconnected, a space having a width at least equal to the minimum space between two lines separated by one line being left free, in a second direction perpendicular to the first direction, on either side of a minimum rectangle containing the first and the second lines.

Claims

1. A method for defining a plurality of parallel lines extending in a first direction in a same level of an integrated circuit at regular intervals, comprising:

forming a first parallel line portion;

forming a second parallel line portion at an uneven number of intervals from the first parallel line portion, wherein;

the first parallel line portion and the second parallel line portion are interconnected in the same level; and

a rectangular surface area defined by the first parallel line portion and the second parallel line portion is separated from any other line of the plurality of lines by at least two intervals.

2. The method of claim 1, wherein a minimum distance (a) between any two lines of the plurality of parallel lines is equal to a width of the first parallel line portion.

3. The method of claim 1, further comprising:

providing at least a predetermined minimum distance (b), in the first direction, between first and second adjacent portions of a single parallel line from among the plurality of parallel lines.

4. The method of claim 1, wherein each of the plurality of parallel lines comprises a length, in the first direction, greater than or equal to a predetermined minimum length (c).

5. A method for manufacturing an integrated circuit level comprising:

etching a plurality of parallel lines extending in a first direction in the integrated circuit level at regular intervals, wherein the plurality of parallel lines are defined according to;

forming a first parallel line portion;

forming a second parallel line portion at an uneven number of intervals from the first parallel line portion, wherein;

the first parallel line portion and the second parallel line portion are interconnected in the same level; and

a rectangular area defined by the first parallel line portion and the second parallel line portion is separated from any other line of the plurality of lines by at least two intervals.

6. The method of claim 5, further comprising:

filling the etched lines with a conductive material to form conductive tracks.

7. The method of claim 5, wherein the etched lines are formed through an etch mask having its contour defined in two lithography steps.

8. The method of claim 5, wherein the etched lines are formed through an etch mask having its contour defined by a step of lithography of a sacrificial layer, a step of conformal deposition of a spacing layer, a step of anisotropic etching of the spacing layer, and a step of etching of remaining portions of the sacrificial layer.