Nanopillar field-effect and junction transistors

• US 8,883,645 B2
• Filed: 07/12/2013
• Issued: 11/11/2014
• Est. Priority Date: 11/09/2012
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Chang, Chieh-Feng, Rajagopal, Aditya, Scherer, Axel
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US13/941,240
• Publication Number:
  US 20140134819A1
• Time in Patent Office: 487 Days
• Field of Search: None
• US Class Current: 438/695
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET

Abstract

Methods for fabrication of nanopillar field effect transistors are described. These transistors can have high height-to-width aspect ratios and be CMOS compatible. Silicon nitride may be used as a masking material. These transistors have a variety of applications, for example they can be used for molecular sensing if the nanopillar has a functionalized layer contacted to the gate electrode. The functional layer can bind molecules, causing an electrical signal in the transistor.

Claims

1. A method for fabricating a nanopillar field effect transistor, the method comprising:

providing a semiconductor substrate;

depositing a first masking material on the semiconductor substrate;

defining a masking pattern on the first masking material;

removing selected regions of the first masking material, based on the masking pattern, thereby exposing selected regions of the semiconductor substrate, based on the masking pattern;

depositing a second masking material on the first masking material and on the semiconductor substrate;

removing the first masking material and unwanted regions of the second masking material, based on the masking pattern;

etching an array of nanopillars in the semiconductor substrate, based on the masking pattern;

depositing silicon nitride on the semiconductor substrate and on the array of nanopillars;

depositing a third masking material on the semiconductor substrate, wherein the height of the third masking material is lower than the height of the array of nanopillars, thereby covering the silicon nitride deposited on the semiconductor substrate but not covering the silicon nitride deposited on the array of nanopillars;

etching the silicon nitride deposited on the array of nanopillars;

removing the third masking material;

oxidizing the array of nanopillars, thereby obtaining a gate oxide layer between the semiconductor substrate and a bottom side of the array of nanopillars;

defining at least one source region and at least one drain region, by doping the semiconductor substrate;

annealing the at least one source region and the at least one drain region;

removing the second masking material;

depositing metal electrodes on the at least one source region, the at least one drain region, and the top of each nanopillar of the array of nanopillars.

2. The method of claim 1, wherein the semiconductor substrate is highly doped.

3. The method of claim 1, wherein the first masking material is PMMA.

4. The method of claim 1, wherein the defining a masking pattern is carried out by electron beam lithography.

5. The method of claim 1, wherein the second masking material is alumina.

6. The method of claim 1, wherein the etching an array of nanopillars is carried out with deep reactive ion etching.

7. The method of claim 1, wherein the depositing of silicon nitride is carried out by low-pressure chemical vapor deposition.

8. The method of claim 1, wherein the third masking material is PMMA.

9. The method of claim 1, wherein the etching the silicon nitride is carried out with phosphoric acid.

10. The method of claim 1, wherein the oxidizing is carried out in a furnace.

11. The method of claim 1, wherein the defining at least one source region and at least one drain region is carried out by focused ion beam lithography.

12. The method of claim 1, wherein the annealing is carried out by electron beam.

13. The method of claim 1, wherein a thickness of the gate oxide is less than 100 nm.

14. The method of claim 1, wherein a height-to-width aspect ratio of the array of nanopillars is greater than 50.

15. The method of claim 1, wherein the shape of each nanopillar of the array of nanopillars comprises a cylindrical shape, a rectangular shape, or a tapered shape.

16. A method for fabricating a nanopillar field effect transistor, the method comprising:

providing a semiconductor substrate, the semiconductor substrate comprising a first semiconductor layer, an insulator layer, and a second semiconductor layer;

depositing a first masking material on the second semiconductor layer;

defining a masking pattern on the first masking material;

removing selected regions of the first masking material, thereby exposing selected regions of the semiconductor substrate, based on the masking pattern;

depositing a second masking material on the first masking material and on the semiconductor substrate;

removing the first masking material and unwanted regions of the second masking material, based on the masking pattern;

etching an array of nanopillars in the semiconductor substrate, based on the masking pattern, wherein the etching is carried out up to a depth of the insulator layer, thereby obtaining a gate oxide layer between the semiconductor substrate and a bottom side of the array of nanopillars;

oxidizing the array of nanopillars;

removing regions of the insulator layer, wherein the regions of the insulator layer are not covered by the array of nanopillars;

defining at least one source region and at least one drain region, by doping the semiconductor substrate;

annealing the at least one source region and the at least one drain region;

removing the second masking material;

depositing metal electrodes on the at least one source region, the at least one drain region, and the top of each nanopillar of the array of nanopillars.

17. The method of claim 16, wherein the first semiconductor layer and the second semiconductor layer are silicon and the insulator layer is silicon oxide.

18. The method of claim 16, wherein a thickness of the insulator layer is chosen to be substantially equal to a desired thickness of the gate oxide, and the thickness of the second semiconductor layer is chosen to be substantially equal to a desired height of the array of nanopillars.

19. The method of claim 16, wherein the first semiconductor layer and/or the second semiconductor layer are highly doped.

20. The method of claim 16, wherein the first masking material is PMMA.

21. The method of claim 16, wherein the defining a masking pattern is carried out by electron beam lithography.

22. The method of claim 16, wherein the second masking material is alumina.

23. The method of claim 16, wherein the etching an array of nanopillars is carried out with deep reactive ion etching.

24. The method of claim 16, wherein the oxidizing is carried out in a furnace.

25. The method of claim 16, wherein the defining at least one source region and at least one drain region is carried out by focused ion beam lithography.

26. The method of claim 16, wherein the annealing is carried out by electron beam.

27. The method of claim 16, wherein a thickness of the insulator layer is less than 100 nm.

28. The method of claim 16, wherein a height-to-width aspect ratio of the array of nanopillars is greater than 50.

29. The method of claim 16, wherein the shape of each nanopillar of the array of nanopillars comprises a cylindrical shape, a rectangular shape, or a tapered shape.