Memory semiconductor device having aligned side surfaces
First Claim
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1. A semiconductor device comprising:
- a semiconductor layer comprising a channel formation region;
a source electrode and a drain electrode over the semiconductor layer and electrically connected to the channel formation region;
a gate electrode over the channel formation region;
a gate insulating layer between the semiconductor layer and the gate electrode; and
an electrode over the gate insulating layer, the electrode overlapping with the source electrode or the drain electrode with the gate insulating layer interposed therebetween,wherein an upper surface of the source electrode and an upper surface of the drain electrode are covered with the gate insulating layer,wherein the source electrode and the drain electrode comprise at least one of a metal, a metal oxide and a metal nitride,wherein a side surface of the semiconductor layer is in contact with the source electrode and the drain electrode, andwherein a portion of a side surface of the gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other.
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Abstract
An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.
120 Citations
20 Claims
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1. A semiconductor device comprising:
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a semiconductor layer comprising a channel formation region; a source electrode and a drain electrode over the semiconductor layer and electrically connected to the channel formation region; a gate electrode over the channel formation region; a gate insulating layer between the semiconductor layer and the gate electrode; and an electrode over the gate insulating layer, the electrode overlapping with the source electrode or the drain electrode with the gate insulating layer interposed therebetween, wherein an upper surface of the source electrode and an upper surface of the drain electrode are covered with the gate insulating layer, wherein the source electrode and the drain electrode comprise at least one of a metal, a metal oxide and a metal nitride, wherein a side surface of the semiconductor layer is in contact with the source electrode and the drain electrode, and wherein a portion of a side surface of the gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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an impurity region provided in a semiconductor substrate; and a first transistor and a second transistor, each of the first transistor and the second transistor comprising; a channel formation region provided in the semiconductor substrate; a gate insulating layer over the channel formation region; a gate electrode over the gate insulating layer, the gate electrode overlapping with the channel formation region; and a source region and a drain region provided in the semiconductor substrate and between which the channel formation region is sandwiched, wherein one of the source region and the drain region is covered by the gate insulating layer while the gate insulating layer is not provided over the other of the source region and the drain region, wherein each of the first transistor and the second transistor includes a portion of the impurity region as the other of the source region and the drain region, and wherein a portion of a side surface of the channel formation region and a portion of a side surface of the gate insulating layer are substantially aligned with each other. - View Dependent Claims (8, 9, 10, 11)
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12. A semiconductor device comprising:
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a first transistor comprising; a first channel formation region provided in a semiconductor substrate; a first gate insulating layer over the first channel formation region; a first gate electrode over the first gate insulating layer, the first gate electrode overlapping with the first channel formation region; and a source region and a drain region provided in the semiconductor substrate and between which the first channel formation region is sandwiched; and a second transistor comprising; a semiconductor layer comprising a second channel formation region; a source electrode and a drain electrode electrically connected to the second channel formation region; a second gate electrode over the second channel formation region; and a second gate insulating layer between the second channel formation region and the second gate electrode, wherein an upper surface of the source electrode and an upper surface of the drain electrode are covered with the second gate insulating layer, wherein the first gate electrode is in direct contact with the source electrode or the drain electrode, wherein the source electrode and the drain electrode comprise at least one of a metal, a metal oxide and a metal nitride, wherein a side surface of the semiconductor layer is in contact with the source electrode and the drain electrode, wherein the first channel formation region and the second channel formation region comprise different semiconductor materials as respective main components, and wherein a portion of a side surface of the second gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification