Semiconductor device and manufacturing method thereof

• US 8,884,284 B2
• Filed: 12/20/2012
• Issued: 11/11/2014
• Est. Priority Date: 12/23/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US13/721,141
• Publication Number:
  US 20130161609A1
• Time in Patent Office: 691 Days
• Field of Search: 349/43, 257/301, 257/E27.11, 257/38, 257/72, 257/59, 438/104, 438/46
• US Class Current: 257/43
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The number of manufacturing steps is reduced to provide a semiconductor device with high productivity and low cost. A semiconductor device with low power consumption and high reliability is provided. A photolithography process for forming an island-shaped semiconductor layer is omitted, and a semiconductor device is manufactured through at least four photolithography processes: a step for forming a gate electrode (including a wiring or the like formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer), a step for forming a contact hole, and a step for forming a pixel electrode. In the step for forming the contact hole, a groove portion is formed, whereby formation of a parasitic transistor is prevented. The groove portion overlaps with the wiring with an insulating layer provided therebetween.

Claims

1. A semiconductor device comprising:

a transistor comprising a gate electrode, a source electrode, a drain electrode, an insulating layer, and a semiconductor layer;

a first wiring electrically connected to the gate electrode;

a second wiring electrically connected to the source electrode;

a pixel electrode electrically connected to the drain electrode;

a capacitor wiring; and

a groove portion,

wherein the semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring,

wherein the groove portion extends beyond edges of the pixel electrode along a direction in which the second wiring extends, and

wherein the groove portion is formed over a portion of the first wiring, a portion of the capacitor wiring, and a portion of the insulating layer.

2. The semiconductor device according to claim 1,

wherein the groove portion crosses the first wiring in a line width direction of the first wiring,

wherein the groove portion crosses the capacitor wiring in a line width direction of the capacitor wiring, and

wherein the groove portion does not have the semiconductor layer, overlaps with the first wiring with the insulating layer provided therebetween, and overlaps with the capacitor wiring with the insulating layer provided therebetween.

3. The semiconductor device according to claim 1, wherein a width of the groove portion is greater than or equal to 1 μ

m.

4. The semiconductor device according to claim 1, wherein the semiconductor layer includes an oxide semiconductor.

5. A semiconductor device comprising:

a first wiring;

a second wiring;

a semiconductor layer;

a pixel electrode;

a first groove portion; and

a second groove portion,

wherein the semiconductor layer overlaps with the first wiring and the pixel electrode,

wherein the first groove portion is positioned over the first wiring and crosses the first wiring,

wherein the second groove portion is positioned between the second wiring and the pixel electrode and extends beyond edges of the pixel electrode along a direction in which the second wiring extends, and

wherein the first groove portion overlaps with the first wiring with an insulating layer provided therebetween.

6. The semiconductor device according to claim 5, wherein the first groove portion and the second groove portion do not have the semiconductor layer.

7. The semiconductor device according to claim 5, wherein the semiconductor layer includes an oxide semiconductor.

8. The semiconductor device according to claim 5, wherein a width of the first groove portion and a width of the second groove portion are respectively greater than or equal to 1 μ

m.

9. The semiconductor device according to claim 5, further comprising:

a first pixel;

a second pixel adjacent to the first pixel; and

a third groove portion between the first pixel and the second pixel,

wherein the first pixel includes the first wiring, the second wiring, the semiconductor layer, the pixel electrode, the first groove portion, and the second groove portion,

wherein the third groove portion does not have the semiconductor layer on a bottom surface of the third groove portion, and

wherein the third groove portion extends beyond edges of the first pixel.

10. A semiconductor device comprising:

a first transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer;

a second transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer;

a first wiring;

a second wiring;

a third wiring;

a pixel electrode;

a first groove portion; and

a second groove portion,

wherein the gate electrode of the first transistor is electrically connected to the first wiring,

wherein one of the source electrode and the drain electrode of the first transistor is electrically connected to the second wiring,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor,

wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to the third wiring,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the pixel electrode,

wherein the semiconductor layer overlaps with the first wiring, the second wiring, the third wiring, and the pixel electrode,

wherein the first groove portion is positioned between the second wiring and the third wiring and over the first wiring and crosses the first wiring,

wherein the second groove portion is positioned between the second wiring and the third wiring and extends beyond edges of the pixel electrode along a direction in which the second wiring extends, and

wherein the first groove portion overlaps with the first wiring with an insulating layer provided therebetween.

11. The semiconductor device according to claim 10, wherein the first groove portion and the second groove portion do not have the semiconductor layer.

12. The semiconductor device according to claim 10, wherein the semiconductor layer includes an oxide semiconductor.

13. The semiconductor device according to claim 10, wherein a width of the first groove portion and a width of the second groove portion are respectively greater than or equal to 1 μ

m.

14. The semiconductor device according to claim 10, further comprising:

a first pixel;

a second pixel adjacent to the first pixel; and

a third groove portion between the first pixel and the second pixel,

wherein the first pixel includes the first transistor, the second transistor, the first wiring, the second wiring, the third wiring, the pixel electrode, the first groove portion, and the second groove portion,

wherein the third groove portion does not have the semiconductor layer on a bottom surface of the third groove portion, and

wherein the third groove portion extends beyond edges of the first pixel.