Semiconductor device having embedded strain-inducing pattern and method of forming the same

• US 8,884,298 B2
• Filed: 03/14/2013
• Issued: 11/11/2014
• Est. Priority Date: 06/25/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Maeda, Shigenobu, Fukutome, Hidenobu, Ko, Young-Gun, Jeong, Joo-Hyun
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US13/826,633
• Publication Number:
  US 20130341631A1
• Time in Patent Office: 607 Days
• Field of Search: 257/347, 438/301
• US Class Current: 257/66
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

Claims

1. A semiconductor device, comprising:

an active region formed in a substrate and having an upper surface, a first side surface, a second side surface opposite the first side surface, and a third side surface in contact with the first and second side surfaces;

a gate electrode covering at least one of the upper surface, the first side surface, and the second side surface; and

a strain-inducing pattern in contact with the third side surface of the active region,

wherein the third surface of the active region includes two or more planes of which a first plane forms an acute angle with respect to the first side surface, and a second plane forms an acute angle with respect to the second side surface.

2. The semiconductor device of claim 1, wherein each of the first and second planes of the active region is perpendicular to the upper surface.

3. The semiconductor device of claim 1, wherein a first edge at which the first and second planes of the active region meet, is perpendicular to the upper surface.

4. The semiconductor device of claim 3, wherein the first edge is overlapped by the gate electrode.

5. The semiconductor device of claim 3, wherein the upper surface of the active region has {110} surface, each of the first and second side surfaces has {100} surface, and each of the first and second planes has {111} surface.

6. The semiconductor device of claim 5, wherein the third side surface of the active region includes a third plane in contact with upper ends of the first and second planes and in contact with the upper surface, wherein the third plane forms an acute angle with respect to the upper surface.

7. The semiconductor device of claim 6, wherein the third plane has {111} surface.

8. The semiconductor device of claim 6, wherein an interface between the active region and the strain-inducing pattern has a trapezoidal shape in a cross-sectional view.

9. The semiconductor device of claim 1, wherein the first and second planes of the active region have a V-shape in a top view.

10. The semiconductor device of claim 1, wherein the third side surface of the active region comprises,

a third plane in contact with upper ends of the first and second planes and in contact with the upper surface;

and

a fourth plane in contact with lower ends of the first and second planes,

wherein the third plane forms an acute angle with respect to the upper surface.

11. The semiconductor device of claim 10, wherein each of the upper surface, first side surface, and second side surface of the active region has {110} surface, and each of the first plane, the second plane, the third plane, and the fourth plane has {111} surface.

12. The semiconductor device of claim 10, wherein the first plane, the second plane, the third plane, and the fourth plane meet at a first corner point.

13. The semiconductor device of claim 10, further comprising:

a second corner point at which the first plane, second plane, and third plane of the active region meet;

a second edge at which the first plane and the second plane meet; and

a third corner point at which the first plane, the second plane, and the fourth plane meet,

wherein the second corner point, the second edge, and the third corner point are aligned perpendicular to the upper surface of the active region.

14. The semiconductor device of claim 10, further comprising:

a fourth corner point at which the first plane, third plane, and fourth plane of the active region meet;

a third edge at which the third plane and the fourth plane meet; and

a fifth corner point at which the second plane, the third plane, and the fourth plane meet,

wherein the fourth corner point, the third edge, and the fifth corner point are aligned parallel to the upper surface of the active region.

15. The semiconductor device of claim 1, wherein the third side surface of the active region comprises,

a fifth plane in contact with the first side surface and in contact with a lower end of the first plane;

and

a sixth plane in contact with the second side surface and in contact with a lower end of the second plane,

wherein the first plane is in contact with the first side surface and the upper surface, and forms an acute angle with respect to each of the first side surface and the upper surface,

the second plane is in contact with the second side surface and the upper surface, and forms an acute angle with respect to each of the second side surface and the upper surface,

the fifth plane forms an acute angle with respect to the first side surface,

the sixth plane forms an acute angle with respect to the second side surface, and

the first plane, the second plane, the fifth plane, and the sixth plane meet to form a sixth corner point.

16. The semiconductor device of claim 15, wherein each of the upper surface, first side surface, and second side surface of the active region has {100} surface, and each of the first plane, the second plane, the fifth plane, and the sixth plane has {111} surface.

17. The semiconductor device of claim 1, wherein the gate electrode covers the first and second side surfaces of the active region.

18. A semiconductor device, comprising:

a pair of strain-inducing patterns formed in a substrate;

an active region formed between the pair of strain-inducing patterns, and having a first side surface and a second side surface opposite the first side surface; and

a gate electrode crossing the active region and covering the first and second side surfaces,

wherein each of interfaces between the active region and the pair of strain-inducing patterns includes two or more planes of which a first plane forms an acute angle with respect to the first side surface, and a second plane forms an acute angle with respect to the second side surface.

19. The semiconductor device of claim 18, further comprising:

an insulating pattern formed between an upper surface of the active region and the gate electrode; and

a gate dielectric layer formed between the active region and the gate electrode.

20. A semiconductor device, comprising:

an active region having a fin portion providing a channel region between opposing source and drain regions;

a gate electrode crossing over the channel region between the opposing source and drain regions; and

first and second strain inducing structures on opposing sides of the gate electrode configured to induce strain on the channel region, each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

21. The device of claim 20 wherein each pair of the facets is directly adjacent to opposing side surfaces of the respective strain inducing structure.

22. The device of claim 21 wherein the pair of facets define respective obtuse angles relative to the opposing side surfaces of the respective strain inducing structure.

23. The device of claim 20 wherein each of the facets obliquely faces opposing interior side walls of the gate electrode crossing over the channel region.

24. The device of claim 23 further comprising:

an oxide layer formed on the opposing interior side walls of the gate electrode crossing over the channel region; and

an insulating layer on an upper interior side wall of the gate electrode crossing over the channel region.

25. The device of claim 20 wherein the pair of {111} crystallographically oriented facets comprises a first pair of facets, wherein the strain inducing structures each include a second pair of facets on a lower surface of the strain inducing structures, wherein each of the second pair of the facets is directly adjacent to the opposing side surfaces of the respective strain inducing structure and directly adjacent to lower surfaces of the respective strain inducing structures.

26. The device of claim 25 further comprising:

a third pair of facets on an upper surface of the strain inducing structure, wherein each of the third pair of the facets is directly adjacent to the opposing side surfaces of the respective strain inducing structure and to upper surfaces of the respective strain inducing structures.

27. The device of claim 26 wherein at least a portion of each of the strain inducing structures extends beneath the gate electrode.

28. The device of claim 20 wherein the pairs of {111} crystallographically oriented facets are included in a pyramid tip shaped surface of the first and second strain inducing structures.

29. The device of claim 28 wherein the pyramid tip shaped surface includes a crest line.

30. The device of claim 20 wherein the pairs of {111} crystallographically oriented facets are included in a Chrysler building tip shaped surface of the first and second strain inducing structures each including 4 directly adjoining facets.