Semiconductor integrated-circuit device with standard cells

• US 8,884,338 B2
• Filed: 09/11/2009
• Issued: 11/11/2014
• Est. Priority Date: 05/13/2009
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Ki Joong
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): BUDD, PAUL A
• Application Number:
  US12/557,995
• Publication Number:
  US 20100289069A1
• Time in Patent Office: 1,887 Days
• Field of Search: 257/202, 257/207, 257/208, 257/E27.108, 257/202.207
• US Class Current: 257/207
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0733 in combination with capacitors only
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H10B 99/22 including field-effect components

Abstract

A semiconductor integrated-circuit device is disclosed. The semiconductor integrated-circuit device uses a filter, which includes a standard capacitor, as a standard cell connecting a memory cell with a logic cell. As such, the semiconductor integrated-circuit device can minimize a glitch phenomenon of power/ground voltages and provide stability of power/ground voltages.

Claims

1. A semiconductor integrated-circuit device divided into a core region in which a plurality of cells is arranged and a peripheral region that does not include the core region, the device comprising:

a plurality of memory cells arranged in a predetermined configuration on the core region;

a plurality of logic cells arranged on the core region and configured to perform a variety of logical functions; and

a plurality of standard cells arranged on a region excepting other regions of the core region, which are occupied by the memory cells and the logic cells, and between the logic cells and configured to connect the logic cells;

wherein the plurality of standard cells each includes a single standard capacitor,

wherein each respective single standard capacitor comprises an upper plate including a plurality of first contact portions and a lower plate including a plurality of second contact portions, and a gate dielectric layer interposed between the upper and lower plates; and

wherein each respective single standard capacitor is configured to connect to adjacent logic cells through a well layer doped with a corresponding n or p type dopant.

2. The semiconductor integrated-circuit device claimed as claim 1, wherein the single standard capacitor includes one of a P-MOS and an N-MOS capacitor.

3. The semiconductor integrated-circuit device claimed as claim 1, wherein the standard cells occupy about 10%˜

30% of an empty space in the semiconductor integrated-circuit device.

4. The semiconductor integrated-circuit device claimed as claim 1, wherein the single standard capacitors have different capacities according to a distance between the logic cells which are positioned in the center of the respective standard cell.

5. The semiconductor integrated-circuit device claimed as claim 1, wherein the memory cells include a memory transistor connected between a respective word line and a respective bit line, and a memory cell capacitor.

6. The semiconductor integrated-circuit device claimed as claim 1, wherein the logic cells consists of only a single logic gate.

7. The semiconductor integrated-circuit device claimed as claim 1, wherein the standard cells are inserted into empty spaces after forming the plurality of logic cells.

8. The semiconductor integrated-circuit device claimed as claim 1, wherein the upper plate of the single standard capacitor is a doped CVD (Chemical Vapor Deposition) poly-silicon film.