Method of making a non-volatile memory (NVM) cell structure

• US 8,884,358 B2
• Filed: 01/24/2013
• Issued: 11/11/2014
• Est. Priority Date: 01/24/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Winstead, Brian A., Kang, Sung-Taeg, Rossow, Marc A.
• Primary Examiner(s): Sefer, A.
• Application Number:
  US13/748,808
• Publication Number:
  US 20140203347A1
• Time in Patent Office: 656 Days
• Field of Search: 257/288, 257/325, 438/267
• US Class Current: 257/325
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/127 Quantum box structures
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator

Abstract

A non-volatile memory device includes a substrate and a charge storage layer. The charge storage layer comprises a bottom layer of oxide, a layer of discrete charge storage elements on the bottom layer of oxide, and a top layer of oxide on the charge storage elements. A control gate is on the top layer of oxide. A surface of the top layer of oxide facing a surface of the control gate is substantially planar.

Claims

1. A non-volatile memory device comprising:

a substrate;

a charge storage layer comprising;

a bottom layer of oxide;

a layer of discrete charge storage elements on the bottom layer of oxide;

a top layer of oxide on the discrete charge storage elements; and

a control gate on the top layer of oxide, wherein a surface of the top layer of oxide facing a surface of the control gate is substantially planar, and wherein a radius of curvature of the top layer of oxide over a majority of the discrete charge storage elements is at least twice a sum of a radius of the discrete charge storage element plus a thickness of the top layer of oxide.

2. The device of claim 1, further comprising:

a select gate, wherein a portion of;

the bottom layer of oxide, the discrete charge storage elements, and the top layer of oxide, are between one side of the control gate and one side of the select gate.

3. The device of claim 1, further comprising:

a thin layer of oxide on an outer surface of the charge storage elements.

4. The device of claim 1, further comprising:

a thickness of the top layer of oxide over at least one of the charge storage elements is less than a diameter of the at least one charge storage element.

5. A method of making a non-volatile memory device comprising:

forming a first electrically insulating material on a substrate;

forming discrete charge storage elements on the first electrically insulating material; and

depositing a second electrically insulating material over the discrete charge storage elements, wherein a top surface of the second electrically insulating material is substantially planar, wherein a radius of curvature of the second electrically insulating material over one of the discrete charge storage elements is at least twice a sum of a radius of the one discrete charge storage element plus a thickness of the second electrically insulating material.

6. The method of claim 5, further comprising forming a control gate over the second electrically insulating material.

7. The method of claim 5, further comprising forming a select gate over a third insulating material.

8. The method of claim 5, further comprising growing an oxide layer on the discrete charge storage elements before depositing the second electrically insulating material.

9. The method of claim 5, wherein a thickness of the second electrically insulating material over at least one of the discrete charge storage elements is less than a diameter of the at least one discrete charge storage element.

10. The method of claim 5, further comprising chemically-mechanically polishing the second electrically insulating material to be substantially planar.

11. The method of claim 5, further comprising depositing a conformal layer of electrically insulating material on the discrete charge storage elements before depositing the second electrically insulating material.

12. The method of claim 5, further comprising etching the second electrically insulating material to be substantially planar.

13. A method comprising:

forming a first oxide layer on a substrate;

forming discrete charge storage elements on the first oxide layer; and

forming a second oxide layer that is planar on the discrete charge storage elements having a thickness that is less than a diameter of the charge storage elements, wherein a radius of curvature of the second oxide layer over the discrete charge storage elements is at least twice a sum of a radius of the discrete charge storage elements plus a thickness of the second oxide layer.

14. The method of claim 13, wherein the diameter of the discrete charge storage elements is between 10 to 20 nanometers and the thickness of the second oxide layer over the charge storage elements is between 6 and 10 nanometers.

15. The method of claim 13, further comprising depositing a conformal oxide layer on the charge storage elements before depositing the second oxide layer.

16. The method of claim 13, further comprising chemically-mechanically polishing the second oxide layer.

17. The method of claim 13, further comprising etching the second oxide layer.