Semiconductor device with improved robustness

• US 8,884,360 B2
• Filed: 02/24/2012
• Issued: 11/11/2014
• Est. Priority Date: 02/24/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Siemieniec, Ralf, Blank, Oliver, Mauder, Anton, Hirler, Franz
• Primary Examiner(s): Weiss, Howard
• Assistant Examiner(s): SKYLES, TIFNEY L
• Application Number:
  US13/404,161
• Publication Number:
  US 20130221427A1
• Time in Patent Office: 991 Days
• Field of Search: 257328-330
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a first contact in low Ohmic contact with a source region of the device and a first portion of a body region of the device formed in an active area of the device, and a second contact in low Ohmic contact with a second portion of the body region formed in a peripheral area of the device. The minimum width of the second contact at a first surface of the device is larger than the minimum width of the first contact at the first surface so that maximum current density during commutating the semiconductor device is reduced and thus the risk of device damage during hard commutating is also reduced.

Claims

1. A semiconductor device, comprising a semiconductor body comprising:

a first surface defining a vertical direction;

a drift region of a first conductivity type comprising a first maximum doping concentration and being arranged below the first surface; and

,

a semiconductor layer of the first conductivity type comprising a second maximum doping concentration which is lower than the first maximum doping concentration, the semiconductor layer adjoining the drift region and being arranged below the drift region, the semiconductor body further comprising in a vertical cross-section;

a first body region of a second conductivity type adjoining the drift region, a source region of the first conductivity type adjoining the first body region and being arranged between the first surface and the first body region;

a vertical trench extending from the first surface at least to the semiconductor layer, adjoining the source region, the first body region and the drift region, and comprising an insulated gate electrode;

a first contact comprising at the first surface a first minimum width and being in low Ohmic contact with the source region and the first body region;

a second body region of the second conductivity type which forms a pn-junction only with the drift region; and

,

a second contact in low Ohmic contact with the second body region and comprising at the first surface a second minimum width which is larger than the first minimum width.

2. The semiconductor device of claim 1, wherein the first contact is formed as a shallow trench contact comprising below the first surface a minimum width substantially matching the first minimum width.

3. The semiconductor device of claim 1, wherein the second contact is formed as a shallow trench contact comprising below the first surface a minimum width substantially matching the second minimum width.

4. The semiconductor device of claim 1, wherein the second body region adjoins in the vertical cross-section the vertical trench, further comprising in the vertical cross-section a further vertical trench extending from the first surface at least to the semiconductor layer, adjoining the source region, the first the body region and the drift region, and comprising an insulated gate electrode.

5. The semiconductor device of claim 4, wherein at least one of the vertical trench and the further vertical trench comprises an insulated field-electrode.

6. The semiconductor device of claim 1, wherein the semiconductor body further comprises an active area and a peripheral area comprising a circumferential trench which extends from the first surface at least to the semiconductor layer and comprises an insulated field electrode surrounding the active area when seen from above, in the vertical cross-section the circumferential trench adjoining the second body region, and the first body region being arranged in the active area.

7. The semiconductor device of claim 6, further comprising in the peripheral area a semiconductor region of the second conductivity type and a neighboring trench field electrode which is in low ohmic contact with the semiconductor region and which is, in the vertical cross-section, separated from the semiconductor body by a dielectric region.

8. The semiconductor device of claim 1, wherein the second minimum width is at least 1.2 times larger than the first minimum width.

9. The semiconductor device of claim 1, wherein the second body region extends to the first surface.

10. A MOSFET, comprising a semiconductor body comprising:

a first surface defining a vertical direction;

a body region; and

,

a drift region forming a pn-junction with the body region, the semiconductor body further comprising in a vertical cross-section;

an active area comprising a source region extending to the first surface and forming a further pn-junction with a first portion of the body region, a first vertical trench which extends from the first surface at least into the drift region, adjoins the first portion of the body region and comprises an insulated gate electrode, and a first contact in low Ohmic contact with the source region and the first portion of the body region, the first contact comprising at the first surface a first minimum width;

a peripheral area comprising a second portion of the body region which extends to the first surface, a second vertical trench which extends from the first surface into the drift region, adjoins the second portion of the body region and comprises an insulated field electrode, and a second contact in low Ohmic contact with the second portion of the body region and comprising at the first surface a second minimum width which is larger than the first minimum width; and

,

a third vertical trench which extends from the first surface into the drift region, adjoins the first portion and the second portion of the body region, and comprises an insulated gate electrode.

11. The MOSFET of claim 10, wherein the first contact is formed as a shallow trench contact comprising below the first surface and in active area a minimum width substantially matching the first minimum width.

12. The MOSFET of claim 10, wherein the second contact is formed as a shallow trench contact comprising below the first surface a minimum width substantially matching the second minimum width.

13. The MOSFET of claim 10, wherein the peripheral area further comprises at least one additional edge-termination structure.

14. The MOSFET of claim 10, wherein a first body contact region comprising a higher maximum doping concentration than the first portion of the body region is arranged between the first portion of the body region and the first shallow trench contact, and wherein a second body contact region comprising a higher maximum doping concentration than the first body contact region is arranged between the second portion of the body region and the second shallow trench contact.

15. The MOSFET of claim 11, wherein the first shallow trench contact is formed in a shallow trench comprising in the active area a first maximum width which is substantially equal to the first minimum width and in the peripheral area a maximum width, measured in the same direction as the first maximum width, which is substantially equal to second minimum width.

16. The MOSFET of claim 12, wherein the second shallow trench contact is formed in a shallow trench at least piece-wise surrounding the active area when seen from above.

17. The MOSFET of claim 10, comprising several third vertical trenches arranged around the active area when seen from above.

18. The MOSFET of claim 10, wherein the active area comprises in the vertical cross-section at least one of a plurality of first portions of the body region, a plurality of first vertical trenches, and a plurality of first contacts.

19. The MOSFET of claim 10, wherein the drift region is of a first conductivity type and comprises a first maximum doping concentration, further comprising a semiconductor layer of the first conductivity type comprising a second maximum doping concentration which is lower than the first maximum doping concentration, the semiconductor layer adjoining the drift region and being arranged below the drift region.

20. The MOSFET of claim 10, further comprising a source metallization arranged on the first surface and in contact with the first contact and the second contact.

21. The MOSFET of claim 10, wherein the second portion of the body region forms a pn-junction only with the drift region.

22. The MOSFET of claim 10, wherein the semiconductor body further comprises a second surface arranged opposite to the first surface and an outer edge extending between the first surface and the second surface, and wherein the peripheral area extends to the outer edge.