Large bit-per-cell three-dimensional mask-programmable read-only memory
First Claim
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1. A three-dimensional mask-programmable read-only memory including a plurality of mask-programmable read-only memory levels stacked above and coupled to a semiconductor substrate, comprising:
- a first memory cell comprising a first quasi-conduction layer;
a second memory cell comprising a second quasi-conduction layer and a resistive layer, wherein said resistive layer is not an insulating layer;
a third memory cell comprising a third quasi-conduction layer different from said first quasi-conduction layer;
wherein said first, second and third memory cells have different current-voltage characteristics.
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Abstract
A large bit-per-cell three-dimensional mask-programmable read-only memory (3D-MPROMB) is disclosed. It can achieve large bit-per-cell (e.g. 4-bpc or more). 3D-MPROMB can be realized by adding resistive layer(s) or resistive element(s) to the memory cells.
42 Citations
10 Claims
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1. A three-dimensional mask-programmable read-only memory including a plurality of mask-programmable read-only memory levels stacked above and coupled to a semiconductor substrate, comprising:
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a first memory cell comprising a first quasi-conduction layer; a second memory cell comprising a second quasi-conduction layer and a resistive layer, wherein said resistive layer is not an insulating layer; a third memory cell comprising a third quasi-conduction layer different from said first quasi-conduction layer; wherein said first, second and third memory cells have different current-voltage characteristics. - View Dependent Claims (2, 3, 4, 5)
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6. A three-dimensional mask-programmable read-only memory including a plurality of mask-programmable read-only memory levels stacked above and coupled to a semiconductor substrate, comprising:
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a first memory cell comprising a first quasi-conduction layer; a second memory cell comprising a second quasi-conduction layer and a resistive layer, wherein said resistive layer has a resistance comparable to said second quasi-conduction layer; a third memory cell comprising a third quasi-conduction layer different from said first quasi-conduction layer; wherein said first, second and third memory cells have different current-voltage characteristics. - View Dependent Claims (7, 8, 9, 10)
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Specification