Guard trench

• US 8,884,381 B2
• Filed: 11/15/2010
• Issued: 11/11/2014
• Est. Priority Date: 11/15/2010
• Status: Expired due to Fees

• Current Assignee: DigitalOptics Corporation MEMS (Adeia Inc.)
• Original Assignee: DigitalOptics Corporation MEMS (Adeia Inc.)
• Inventors: Jain, Ankur, Calvet, Robert J., Gutierrez, Roman C.
• Primary Examiner(s): Lee, Jae
• Application Number:
  US12/946,495
• Publication Number:
  US 20120119325A1
• Time in Patent Office: 1,457 Days
• Field of Search: 257/414, 257/415
• US Class Current: 257/414
• CPC Class Codes: B81B 2203/033 Trenches
• CPC Class Codes: B81C 1/00571 Avoid or control under-cutting
• CPC Class Codes: G03B 2205/0061 using piezoelectric actuators
• CPC Class Codes: G03B 3/10 Power-operated focusing

Abstract

A device may comprise a substrate formed of a first semiconductor material, a first trench formed in the substrate, a second trench formed in the substrate proximate the first trench, an oxide layer formed in the first trench and the second trench, and a second semiconductor material formed upon the oxide layer. The oxide layer in the second trench may be adapted to mitigate undercut of the oxide layer in the first trench during an etching process.

Claims

1. A device comprising:

a substrate formed of a first semiconductor material;

a guard trench formed in the substrate;

a first trench formed proximate the guard trench and disposed on a first side of the guard trench;

an oxide layer formed at least partially in the guard trench, wherein the oxide layer is disposed on two opposing sidewalls of the guard trench and extends continuously from the guard trench to the first trench; and

a second semiconductor material formed upon the oxide layer,

wherein the oxide layer comprises an undercut on a second side of the guard trench that is opposite the first side.

2. The device as recited in claim 1, wherein the oxide layer in the guard trench defines a barrier that inhibits an etchant from etching the oxide layer in the first trench.

3. The device as recited in claim 1, wherein the second semiconductor material includes a first portion disposed in the guard trench and a second portion disposed in the first trench.

4. The device as recited in claim 1, wherein the oxide layer in the guard trench prevents the second semiconductor material from contacting the substrate and causing an electrical short.

5. The device as recited in claim 3, wherein the guard trench is deeper than the first trench.

6. The device as recited in claim 1, wherein the guard trench extends completely through the substrate.

7. The device as recited in claim 3, wherein the guard trench and the first trench are substantially parallel with respect to one another.

8. The device as recited in claim 3, wherein the guard trench and the first trench are substantially non-parallel with respect to one another.

9. The device as recited in claim 3, wherein the guard trench and the first trench are formed by a deep reactive-ion etching (DRIE) process.

10. The device as recited in claim 1, wherein the first semiconductor material comprises single crystalline silicon.

11. The device as recited in claim 1, wherein the second semiconductor material comprises polysilicon.

12. An electronic device comprising the device of claim 1.

13. A system comprising:

an actuator device comprising a substrate formed of a first semiconductor material;

a guard trench formed in the substrate;

a first trench formed proximate the guard trench and disposed on a first side of the guard trench;

an oxide layer formed in part in the guard trench, wherein the oxide layer is disposed on two opposing sidewalls of the guard trench and extends from the guard trench to the first trench; and

a second semiconductor material formed upon the oxide layer,

wherein the oxide layer comprises an undercut on a second side of the guard trench that is opposite to the first side.

14. The system as recited in claim 13, wherein the oxide layer in the guard trench defines a barrier that inhibits an etchant from etching the oxide layer in the first trench.

15. The system as recited in claim 13, wherein the second semiconductor material includes a first portion disposed in the guard trench and a second portion disposed in the first trench.

16. The system as recited in claim 13, wherein the oxide layer in the guard trench prevents the second semiconductor material from contacting the substrate and causing an electrical short.

17. The system as recited in claim 15, wherein the guard trench is deeper than the first trench.

18. The system as recited in claim 13, wherein the guard trench extends completely through the substrate.

19. The system as recited in claim 15, wherein the guard trench and the first trench are substantially parallel with respect to one another.

20. The system as recited in claim 15, wherein the guard trench and the first trench are substantially non-parallel with respect to one another.

21. The system as recited in claim 15, where the guard trench and the first trench are formed by a deep reactive-ion etching (DRIE) process.

22. The system as recited in claim 13, wherein the first semiconductor material comprises single crystalline silicon.

23. The system as recited in claim 13, wherein the second semiconductor material comprises polysilicon.

24. An electronic device comprising the system of claim 13.

25. A method, comprising:

forming a guard trench in a substrate formed of a first semiconductor material;

forming a first trench proximate the guard trench on a first side of the guard trench;

forming an oxide layer at least partially in the guard trench, wherein the oxide layer is disposed on two opposing sidewalls of the guard trench and extends continuously from the guard trench to the first trench;

forming a second semiconductor material upon the oxide layer; and

etching a portion of the oxide layer,

wherein the etching forms an undercut, beneath the second semiconductor material that extends at least partially into the guard trench, on a second side of the guard trench that is opposite to the first side.

26. The method as recited in claim 25, further comprising, with the oxide layer in the guard trench, preventing etching of a portion of the oxide layer in the first trench.

27. The method as recited in claim 25, wherein a portion of the second semiconductor material is formed on the portion of the oxide layer in the first trench.