Inductor device and fabrication method

• US 8,884,399 B2
• Filed: 11/30/2012
• Issued: 11/11/2014
• Est. Priority Date: 06/06/2012
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Cheng, Jenhao, Wang, Xining, Liu, Ling
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US13/690,378
• Publication Number:
  US 20130328164A1
• Time in Patent Office: 711 Days
• Field of Search: 257/531
• US Class Current: 257/531
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel.

Claims

1. An inductor device comprising:

a semiconductor substrate;

a first planar spiral wiring disposed over the semiconductor substrate;

a second planar spiral wiring disposed over the first planar spiral wiring; and

a third planar spiral wiring disposed over the second planar spiral wiring,

wherein each planar layer of the first, the second, and the third planar spiral wirings includes an outer spiral metal wiring and, an inner spiral metal wiring including at least two isolated sub-metal-lines each connecting to the outer spiral metal wiring such that the outer spiral metal wiring and the inner spiral metal wiring are connected in series in each corresponding planar layer, and the outer spiral metal wiring surrounds the inner spiral metal wiring in each corresponding planar layer, and

wherein one sub-metal-line of the at least two isolated sub-metal-lines in each planar layer of the first, the second, and the third planar spiral wirings is connected to one another, and the outer spiral metal wiring in the first planar spiral wiring is connected to the outer spiral metal wiring in the third planar spiral wiring such that the first and the third planar spiral wirings are configured in parallel and the second planar spiral wiring is configured in series with the first and the third planar spiral wirings configured in parallel.

2. The device of claim 1, further including:

a first dielectric layer disposed between the semiconductor substrate and the first planar spiral wiring;

a second dielectric layer disposed between the first planar spiral wiring and the second planar spiral wiring; and

a third dielectric layer disposed between the second planar spiral wiring and the third planar spiral wiring.

3. The device of claim 1, further including:

a first conductive plug connecting the one sub-metal-line of the at least two first sub-metal-lines in the first planar spiral wiring to the one sub-metal-line of the at least two sub-metal-lines in the second planar spiral wiring; and

a second conductive plug connecting the one sub-metal-line of the at least two first sub-metal-lines in the second planar spiral wiring to the one sub-metal-line of the at least two sub-metal-lines in the third planar spiral wiring.

4. The device of claim 1, wherein the inner spiral metal wiring in the first, the second, or the third planar spiral wiring includes about 2 to about 10 isolated sub-metal-lines.

5. The device of claim 1, wherein the outer spiral metal wiring in the first, the second, or the third planar spiral wiring includes about 1 to about 10 isolated sub-metal-lines.

6. The device of claim 1, wherein a distance between adjacent sub-metal-lines in each of the first, the second, and the third planar spiral wirings is about 0.001 μ

m to about 100 μ

m.

7. The device of claim 1, wherein each sub-metal-line in the first, the second, and the third planar spiral wirings has a width of about 0.1 μ

m to about 100 μ

m.

8. The device of claim 1, wherein the first, the second, or the third planar spiral wiring is made of a material including copper or aluminum, and has a shape selected from a quadrilateral, hexagonal, octagonal or circular shape.

9. The device of claim 1, wherein the first, the second, or the third planar spiral wiring has a thickness of about 0.1 μ

m to about 100 μ

m, and an inner radius of about 5 μ

m to about 1 m.

10. The device of claim 1, wherein the outer spiral metal wiring in the first, the second, or the third planar spiral wiring is made by a single wire of copper and has a thickness of about 0.1 μ

m to about 100 μ

m.

11. The device of claim 1, wherein only an end of the at least two isolated sub-metal-lines of the inner spiral metal wiring is connected to the outer spiral metal wiring.

12. The device of claim 1, wherein, in each planar layer of the first, the second, and the third planar spiral wirings, the outer spiral metal wiring comprises a single conductive wire having a width greater than a width of any of the at least two isolated sub-metal-lines in each corresponding planar layer.

13. An inductor device comprising:

a semiconductor substrate;

a first planar spiral wiring disposed over the semiconductor substrate;

a second planar spiral wiring disposed over the first planar spiral wiring; and

a third planar spiral wiring disposed over the second planar spiral wiring,

wherein;

a first planar layer of the first planar spiral wiring includes an outer spiral metal wiring including at least two isolated sub-metal-lines, and surrounding an inner spiral metal wiring, such that the outer spiral metal wiring and the inner spiral metal wiring are connected in series, the outer spiral metal wiring in the first planar layer is connected to a first outer contact layer, and the inner spiral metal wiring in the first planar layer is connected to a first inner contact layer,

a second planar layer of the second planar spiral wiring includes an outer spiral metal wiring surrounding an inner spiral metal wiring including at least two isolated sub-metal-lines, such that the outer spiral metal wiring and the inner spiral metal wiring are connected in series, an inner sub-metal line of the inner spiral metal wiring in the second planar layer is connected to a second inner contact layer, and an outer sub-metal line of the inner spiral metal wiring is connected to a second outer contact layer, and

a third planar layer of the third planar spiral wiring includes an outer spiral metal wiring including at least two isolated sub-metal-lines, and surrounding an inner spiral metal wiring, such that the outer spiral metal wiring and the inner spiral metal wiring are connected in series, the outer spiral metal wiring in the third planar layer is connected to a third outer contact layer, and the inner spiral metal wiring in the third planar layer is connected to a third inner contact layer,

wherein;

the first outer contact layer in the first planar layer, the second inner contact layer in the second planar layer, and the third outer contact layer in the third planar layer are connected with one another by a first conductive plug, and

the first inner contact layer in the first planar layer, the second outer contact layer in the second planar layer, and the third inner contact layer in the third planar layer are connected with one another by a second conductive plug,

such that the first and the third planar spiral wirings are configured in parallel and the second planar spiral wiring is configured in series with the first and the third planar spiral wirings configured in parallel.

14. The device of claim 13, further including:

a first dielectric layer disposed between the semiconductor substrate and the first planar spiral wiring;

a second dielectric layer disposed between the first planar spiral wiring and the second planar spiral wiring; and

a third dielectric layer disposed between the second planar spiral wiring and the third planar spiral wiring.

15. The device of claim 13, wherein a distance between adjacent sub-metal-lines in each of the first, the second, and the third planar spiral wirings is about 0.001 μ

m to about 100 μ

m.

16. The device of claim 13, wherein each sub-metal-line in the first, the second, and the third planar spiral wirings has a width of about 0.1 μ

m to about 100 μ

m.

17. The device of claim 13, wherein the first, the second, or the third planar spiral wiring is made of a material including copper or aluminum, and has a shape selected from a quadrilateral, hexagonal, octagonal or circular shape.

18. The device of claim 13, wherein the first, the second, or the third planar spiral wiring has a thickness of about 0.1 μ

m to about 100 μ

m, and an inner radius of about 5 μ

m to about 1 m.