Semiconductor die array structure

• US 8,884,403 B2
• Filed: 12/30/2010
• Issued: 11/11/2014
• Est. Priority Date: 06/19/2008
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Co, Reynaldo, Melcher, DeAnn Eileen, Pan, Weiping, Villavicencio, Grant
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): BACHNER, ROBERT G
• Application Number:
  US12/982,376
• Publication Number:
  US 20110101505A1
• Time in Patent Office: 1,412 Days
• Field of Search: 257/620, 257/782, 257/787, 257/797, 257/E23.179, 257/626, 257/E21.599, 257/E23.133, 257/88, 257/59, 257/E21.602, 257/72, 257/99, 257/40, 257/71, 257/98, 257/E33.053, 257/57, 257/659, 257/690, 257/774, 257/43, 438/462, 438/34, 438/463, 438/158, 438/122, 438/127, 438/29, 438/118, 438/342, 438/396, 438/624, 438/675
• US Class Current: 257/620
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 24/27 Manufacturing methods
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

Claims

1. A structure, comprising:

a support having a surface;

an array of blocks or of rows of semiconductor die extending in at least one direction parallel to active sides of the die, each of the blocks or the rows of the die overlying the surface of the support and having positions maintained relative to one another thereon, the blocks or the rows of the die including at least a first block or first row thereof being fully separated from a second block or second row thereof at a first street disposed between first interconnect sidewalls of the die of the first block or the first row and second sidewalls of the die of the second block or the second row facing the first interconnect sidewalls, and the die in each block or in each row being connected by wafer material in a second set of streets,

and a conformal electrically insulative film applied to surfaces of the die,

said conformal electrically insulative film at least partially overlying active sides of the die, covering interconnect sidewalls and second sidewalls of the die at the first street, said conformal electrically insulative film overlying the wafer material connecting the die in each of the second set of streets.

2. The structure of claim 1, wherein said conformal electrically insulative film comprises a parylene.

3. The structure of claim 1, wherein said conformal electrically insulative film overlies interconnect margins of respective die thereof.

4. The structure of claim 3 wherein said conformal electrically insulative film comprises a parylene.

5. The structure of claim 3, having an opening through the conformal electrically insulative film exposing a surface of an interconnect pad of a die of the plurality of the blocks or the rows of die.

6. The structure of claim 1, wherein the array of blocks or rows of die are partially separated by at least one trench extending along a street of the second set of streets, and said conformal electrically insulative film overlies walls of the at least one trench.

7. The structure of claim 2, wherein the array of blocks or rows of die are partially separated by at least one trench extending along a street of the second set of streets, and said conformal electrically insulative film overlies walls of the at least one trench.

8. The structure of claim 5, wherein said conformal electrically insulative film comprises a parylene, the array of blocks or rows of die are partially separated by at least one trench extending along a street of the second set of streets, and said conformal electrically insulative film overlies walls of the at least one trench.