Etch depth determination structure

• US 8,884,406 B2
• Filed: 09/13/2011
• Issued: 11/11/2014
• Est. Priority Date: 03/23/2007
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lou, Yingying, Li, Tiesheng, Wang, Yu, Bhalla, Anup
• Primary Examiner(s): Parendo, Kevin
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US13/231,872
• Publication Number:
  US 20120001176A1
• Time in Patent Office: 1,155 Days
• Field of Search: 257/642, 257/401, 257/330, 438/14, 438/16, 216/59
• US Class Current: 257/642
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device wafer includes a test structure. The test structure includes a layer of material having an angle-shaped test portion disposed on at least a portion of a surface of the semiconductor wafer. A ruler marking on the surface of the semiconductor wafer proximate the test portion is adapted to facilitate measurement of a change in length of the test portion.

Claims

1. A semiconductor device wafer comprising a test structure wherein said test structure further comprises:

a layer of material comprising a test portion with at least one angular shape at one side of the test portion disposed on at least an exposed portion of a top surface of the semiconductor wafer;

a ruler marking on the surface of the semiconductor wafer proximate the test portion, wherein the ruler marking is adapted to facilitate measurement of a change in length of the test portion; and

a trench formed in the substrate, wherein the layer of material fills at least part of the trench.

2. The wafer of claim 1 further comprising a transparent oxide material disposed over a portion of the layer of material.

3. The wafer of claim 1, wherein the test portion comprises a portion having a tip angle θ

.

4. The wafer of claim 1 wherein the layer of material comprises a polysilicon material.