Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture

• US 8,884,422 B2
• Filed: 12/31/2009
• Issued: 11/11/2014
• Est. Priority Date: 12/31/2009
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Inventors: Goh, Kim-Yong, Luan, Jing-En
• Primary Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US12/651,365
• Publication Number:
  US 20110156250A1
• Time in Patent Office: 1,776 Days
• Field of Search: None
• US Class Current: 257/690
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1052 Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer. The layer of mold compound has a back-ground surface at which a portion of each of the upper solder balls is exposed, for electrical contact with an upper package. Each of the lower redistribution contact pads has a lower solder ball a coupled thereto.

Claims

1. A wafer, comprising:

a rigid redistribution layer on the wafer having a plurality of sections, each section including;

a first plurality of contact pads positioned on a first side of the redistribution layer,

a second plurality of contact pads positioned on a second side of the redistribution layer, and

a plurality of conductive traces, each extending in the redistribution layer and placing two or more of the contact pads of the first and second pluralities of contact pads in electrical communication;

a plurality of semiconductor dice, each of the semiconductor die having a third plurality of contact pads on a first surface, the semiconductor die being positioned with its first surface facing the first side of a respective section of the redistribution layer, with a fan-out portion of the redistribution layer extending beyond the respective semiconductor die in at least one direction parallel to the first side, each fan-out portion of the redistribution layer including a first set of contact pads of the first plurality of contact pads, wherein a second set of contact pads of the first plurality of contact pads is located proximate the semiconductor die, and wherein the first set of contact pads are electrically isolated from the third plurality of contact pads on the first surface of the respective semiconductor die;

a plurality of solder connectors placing each of the third plurality of contact pads of a respective die in electrical communication with a respective one of the second set of the first plurality of contact pads;

a plurality of solder balls coupled to the second plurality of contact pads, respectively, on the fan-out portion of the redistribution layer;

an encapsulating layer positioned on the first side of the redistribution layer and encapsulating side surfaces of the semiconductor die, side surfaces of the plurality of solder balls, and entire side surfaces of the plurality of solder connectors, each of the plurality of solder balls having an upper surface that is coplanar with an upper surface of the encapsulating layer and a second surface of the semiconductor die and

a spacing between each of the semiconductor die indicative of a kerf line for separating the semiconductor die into individual packages.

2. The wafer of claim 1, further comprising a semiconductor package positioned over the upper surface of the encapsulating layer, and having a plurality of contact pads, each having a solder contact placing the respective one of the contact pads of the semiconductor package in electrical communication with a corresponding one of the plurality of solder balls.

3. The wafer of claim 1, further comprising a plurality of solder balls coupled to respective ones of the second plurality of contact pads.

4. The wafer of claim 1, wherein the redistribution layer further includes a first dielectric layer and a second dielectric layer.

5. The wafer of claim 2, wherein the semiconductor package is spaced over and apart from the second surface of the semiconductor die.

6. A device comprising:

a rigid redistribution layer having a first surface having a first portion with a first set of first contacts pads and a second fan-out portion with a second set of first contact pads;

a plurality of first and second solder connectors, the plurality of first solder connectors being located on the first set of first contact pads of the redistribution layer, the plurality of second solder connectors being located on the second set of first contact pads of the redistribution layer;

a semiconductor die having a first surface and a second surface, the first and second surfaces being connected by side surfaces, the first surface of the semiconductor die being positioned on the first portion of the first surface of the redistribution layer, the semiconductor die having a plurality of second contact pads on the first surface and in electrical communication with a respective one of the first set of first contact pads of the redistribution layer via the plurality of first solder connectors, the plurality of second contact pads being electrically isolated from the second set of first contact pads; and

encapsulating material positioned on the first surface of the redistribution layer and encapsulating side surfaces of the semiconductor die and entire side surfaces of the plurality of first and second solder connectors, each of the plurality of first and second solder connectors, the encapsulating layer, and semiconductor die having a common coplanar surface.

7. The device of claim 6, further comprising a semiconductor package positioned over the upper surface of the encapsulating layer, the semiconductor package having a plurality of contact pads, each having a solder contact placing the respective one of the contact pads of the semiconductor package in electrical communication with a corresponding one of the plurality of second solder connectors.

8. The device of claim 7, wherein the semiconductor package is spaced over and apart from the second surface of the semiconductor die.