Semiconductor package with single sided substrate design and manufacturing methods thereof

• US 8,884,424 B2
• Filed: 09/23/2013
• Issued: 11/11/2014
• Est. Priority Date: 01/13/2010
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Su, Yuan-Chang, Huang, Shih-Fu, Chen, Chia-Cheng, Chen, Tzu-Hui, Chen, Kuang-Hsiung, Hsieh, Pao-Ming, Lee, Ming Chiang, Appelt, Bernd Karl
• Primary Examiner(s): Clark, S.V.
• Application Number:
  US14/033,673
• Publication Number:
  US 20140021636A1
• Time in Patent Office: 414 Days
• Field of Search: 257/700, 257/701, 257/778, 257/698
• US Class Current: 257/700
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32057 in side view
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/28 : Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/296 : Organo-silicon compounds
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15183 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Claims

1. A multilayer substrate, comprising:

a first outer conductive patterned layer;

a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads;

a second outer conductive patterned layer;

a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads; and

a plurality of inner layers disposed between the first outer conductive patterned layer and the second outer conductive patterned layer, each of the plurality of inner layers electrically connected with at least one of the first outer conductive patterned layer and the second outer conductive patterned layer, and each of the plurality of inner layers including;

an inner conductive patterned layer;

a plurality of inner conductive posts formed adjacent to the inner conductive patterned layer; and

an inner dielectric layer;

wherein the inner conductive patterned layer and the plurality of inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the plurality of inner conductive posts is exposed from the inner dielectric layer; and

wherein the inner dielectric layer includes a fiber-reinforced resin material, and fibers adjacent to the inner conductive posts are pushed along vertically extending directions of the inner conductive posts and away from the inner conductive patterned layer.

2. The multilayer substrate of claim 1, further comprising:

an outer dielectric layer disposed between the first insulating layer and a first one of the plurality of inner layers; and

a plurality of outer conductive posts extending through the outer dielectric layer and electrically connecting the first outer conductive patterned layer with the inner conductive patterned layer of the first one of the plurality of inner layers.

3. The multilayer substrate of claim 2, wherein one of the plurality of outer conductive posts is aligned with a corresponding one of the plurality of inner conductive posts on each of the plurality of inner layers, such that one of the first set of pads is electrically connected to one of the second set of pads.

4. The multilayer substrate of claim 1, wherein, in each of the plurality of inner layers, one surface of the inner conductive patterned layer is aligned with a first surface of the inner dielectric layer.

5. The multilayer substrate of claim 4, wherein, in each of the plurality of inner layers, one surface of each of the plurality of inner conductive posts is aligned with a second surface of the inner dielectric layer.

6. A multilayer substrate, comprising:

a plurality of inner layers, each including;

an inner conductive patterned layer;

a plurality of inner conductive posts formed adjacent to the inner conductive patterned layer; and

an inner dielectric layer;

wherein the inner conductive patterned layer and the plurality of inner conductive posts are embedded in the inner dielectric layer; and

wherein an uppermost inner layer defines a plurality of openings in the inner dielectric layer of the uppermost inner layer, and at least one of the plurality of openings exposes a top recessed surface of one of the plurality of inner conductive posts of the uppermost inner layer;

an intermediary layer adjacent to a lowermost inner layer, including;

an intermediary dielectric layer; and

a plurality of intermediary conductive posts recessed from a surface of the intermediary dielectric layer;

a first patterned outer conductive layer disposed adjacent to the uppermost inner layer and extending into the at least one of the plurality of openings to contact the top recessed surface of the one inner conductive post; and

a second patterned outer conductive layer disposed adjacent to the intermediary layer and contacting the intermediary conductive posts.

7. The multilayer substrate of claim 6, further comprising:

a pad disposed over the first patterned outer conductive layer and disposed above the one inner conductive post; and

an outer dielectric layer exposing the pad.

8. The multilayer substrate of claim 6, further comprising:

a pad disposed over the second patterned outer conductive layer and positioned below one of the plurality of intermediary conductive posts; and

an outer dielectric layer exposing the pad.

9. A multilayer substrate, comprising:

a plurality of inner layers, each including;

an inner conductive patterned layer;

a plurality of inner conductive posts formed adjacent to the inner conductive patterned layer; and

an inner dielectric layer;

wherein the inner conductive patterned layer and the plurality of inner conductive posts are embedded in the inner dielectric layer;

an intermediary layer including;

an intermediary conductive patterned layer; and

an intermediary dielectric layer defining a plurality of openings;

wherein each of the plurality of openings exposes a portion of the intermediary conductive patterned layer; and

a first patterned outer conductive layer disposed adjacent to the intermediary layer and extending into at least one of the plurality of openings to contact the intermediary conductive patterned layer.

10. The multilayer substrate of claim 9, further comprising:

a pad disposed over the first patterned outer conductive layer, positioned in alignment with one of the plurality of inner conductive posts; and

an outer dielectric layer exposing the pad.

11. The multilayer substrate of claim 9, further comprising:

a first lower dielectric layer defining a plurality of openings exposing the inner conductive patterned layer of one of the plurality of inner layers;

a conductive material extending into at least one of the plurality of openings and contacting the exposed inner conductive patterned layer;

a pad disposed over the conductive material; and

a second lower dielectric layer exposing the pad.

12. A substrate, comprising

a first patterned conductive layer having an upper surface;

a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric layer exposing a portion of the first patterned conductive layer to form a plurality of first contact pads;

a second patterned conductive layer below the first patterned conductive layer and having a lower surface;

a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer,

wherein;

the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer; and

the second patterned conductive layer includes a plurality of second contact pads exposed by the second dielectric layer; and

a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to a corresponding one of the plurality of second contact pads through a corresponding one of the plurality of openings in the second dielectric layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the second dielectric layer.

13. The substrate of claim 12, wherein at least one of the plurality of conductive posts defines a cavity, and wherein the cavity is filled by a part of the first dielectric layer.

14. The substrate of claim 12, wherein:

the second dielectric layer has a lower surface; and

the lower surface of the second patterned conductive layer is recessed from the lower surface of the second dielectric layer.

15. The substrate of claim 12, wherein each of the plurality of conductive posts has an upper surface having a first area and a lower surface having a second area, and the first area is larger than the second area.

16. The substrate of claim 12, wherein the first patterned conductive layer includes a first conductive layer, a second conductive layer, and a seed layer therebetween.

17. A semiconductor package, comprising:

a substrate including;

a first patterned conductive layer having an upper surface;

a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric layer exposing a part of the first patterned conductive layer to form a plurality of first contact pads;

a second patterned conductive layer below the first patterned conductive layer and having a lower surface;

a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein;

the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer; and

the second patterned conductive layer includes a plurality of second contact pads and at least a trace;

a third dielectric layer disposed on the second dielectric layer, the third dielectric layer exposing the second contact pads and covering the trace; and

a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to a corresponding one of the plurality of second contact pads through a corresponding one of the plurality of openings in the second dielectric layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the second dielectric layer;

a die electrically connected to the plurality of first contact pads; and

a package body covering the first patterned conductive layer and the die.