Process of ultra thick trench etch with multi-slope profile

• US 8,884,441 B2
• Filed: 02/18/2013
• Issued: 11/11/2014
• Est. Priority Date: 02/18/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fan, Chun-Liang, Tsai, Kuan-Chi, Hsueh, Chih-Hung, Wang, Wei-Te, Chen, Shao-Yu
• Primary Examiner(s): Nhu, David
• Application Number:
  US13/769,441
• Publication Number:
  US 20140231955A1
• Time in Patent Office: 631 Days
• Field of Search: 257/774, 257/764, 257/760, 257/649, 257/622, 257/396, 257/293, 257/146
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.

Claims

1. An integrated chip (IC) having an ultra-thick metal layer, comprising:

an inter-level dielectric layer disposed above a substrate and having a cavity with a sidewall comprising a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape; and

an ultra-thick metal layer disposed within the cavity, wherein the rounded shape of the cavity reduces stress between the inter-level dielectric layer and the ultra-thick metal layer.

2. The integrated chip of claim 1, wherein the plurality of sections comprise:

a first section having a first slope; and

a second section, located at a greater distance from the substrate than the first section, and having a second slope that is larger than the first slope.

3. The integrated chip of claim 1,

wherein the different slopes produce different sidewall angles between the plurality of sections and the substrate;

and

wherein the different sidewall angles are separated by an angular difference of greater than 5°

.

4. The integrated chip of claim 1, wherein the ultra-thick metal layer comprises copper.

5. The integrated chip of claim 1, wherein the ultra-thick metal layer has a height of greater than 1 micron.

6. The integrated chip of claim 1, further comprising:

a titanium barrier layer disposed between the inter-level dielectric layer and the ultra-thick metal layer.

7. The integrated chip of claim 1, wherein the inter-level dielectric layer comprises oxide.

8. The integrated chip of claim 1, wherein the ultra-thick metal layer is part of an integrated inductor.

9. An integrated chip (IC) having an ultra-thick copper metal layer, comprising:

an inter-level dielectric layer disposed above a substrate and having a cavity with a sidewall comprising a plurality of sections, wherein the plurality of sections form sidewall angles with respect to the substrate that increase as a distance of a section from the substrate increases, thereby giving the cavity a rounded shape; and

an ultra-thick copper metal layer disposed within the cavity, wherein the rounded shape of the cavity reduces stress between the inter-level dielectric layer and the ultra-thick copper metal layer.

10. The integrated chip of claim 9, wherein the sidewall angles are separated by an angular difference of greater than 5°

.

11. The integrated chip of claim 9, wherein the ultra-thick copper metal layer has a height of greater than 1 micron.

12. The integrated chip of claim 9, further comprising:

a titanium barrier layer disposed between the inter-level dielectric layer and the ultra-thick copper metal layer.

13. The integrated chip of claim 9, wherein the inter-level dielectric layer comprises oxide.