Substrate for semiconductor package and process for manufacturing

• US 8,884,443 B2
• Filed: 05/16/2013
• Issued: 11/11/2014
• Est. Priority Date: 07/05/2012
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lee, Chun-Che, Wang, Sheng-Ming, Chen, Tien-Szu
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US13/895,704
• Publication Number:
  US 20140008814A1
• Time in Patent Office: 544 Days
• Field of Search: 257/778, 257/737, 257/738, 438/622
• US Class Current: 257/774
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/48 Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/16055 being circular or elliptic
• CPC Class Codes: H01L 2224/16057 in side view
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3142 : Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457

Abstract

A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Claims

1. A package substrate, comprising:

a dielectric layer;

a first circuit layer disposed on or in the dielectric layer;

a plurality of pillars disposed on the first circuit layer, wherein each of the pillars has a top surface adapted for making external electrical connection, and the top surfaces of the pillars are substantially coplanar with each other;

a second circuit layer; and

a plurality of interconnection metals;

wherein the dielectric layer has a plurality of openings, and the interconnection metals are disposed in the openings of the dielectric layer to connect the second circuit layer and the first circuit layer.

2. The package substrate of claim 1, further comprising a protection layer disposed on the first circuit layer, the protection layer having an opening to expose a portion of the first circuit layer and the pillars.

3. The package substrate of claim 1, wherein the first circuit layer is embedded in the dielectric layer and the second circuit layer is disposed on the dielectric layer.

4. The package substrate of claim 1, wherein the second circuit layer is embedded in the dielectric layer and the first circuit layer is disposed on the dielectric layer.

5. The package substrate of claim 1, wherein a coplanarity of the top surfaces of the pillars is ±

3 μ

m.

6. A package substrate, comprising:

a dielectric layer having an upper surface;

a first circuit layer disposed on or in the dielectric layer;

a plurality of pillars disposed on the first circuit layer, wherein heights of the pillars are substantially equal, wherein the heights are defined as the distance between a top end of each of the pillars and the upper surface of the dielectric layer;

a second circuit layer; and

a plurality of interconnection metals;

wherein the dielectric layer has a plurality of openings, and the interconnection metals are disposed in the openings of the dielectric layer to connect the second circuit layer and the first circuit layer.

7. The package substrate of claim 6, wherein a difference between a greatest pillar height and a least pillar height is less than 6 μ

m.

8. The package substrate of claim 6, further comprising a protection layer disposed on the first circuit layer, wherein the protection layer has at least one opening, and the pillars are disposed within the at least one opening.

9. The package substrate of claim 6, wherein the first circuit layer is embedded in the dielectric layer and the second circuit layer is disposed on the dielectric layer.

10. The package substrate of claim 6, wherein the second circuit layer is embedded in the dielectric layer and the first circuit layer is disposed on the dielectric layer.

11. A process for making a package substrate, comprising:

providing a dielectric layer with a first circuit layer disposed thereon or therein, comprising;

providing a carrier with a second circuit layer disposed thereon;

forming the dielectric layer on the second circuit layer, wherein the dielectric layer has a plurality of openings to expose the second circuit layer;

forming the first circuit layer on the dielectric layer and a plurality of interconnection metals in the openings of the dielectric layer to connect the second circuit layer and the first circuit layer; and

removing the carrier;

forming a photoresist pattern adjacent to the first circuit layer, wherein the photoresist pattern has a plurality of openings;

forming a plurality of pillars in the openings of the photoresist pattern, wherein the pillars are electrically connected to the first circuit layer;

planarizing the pillars so that each of the pillars has a top surface, and the top surfaces of the pillars are substantially coplanar with each other; and

removing the photoresist pattern.

12. The process of claim 11, wherein the photoresist pattern is formed on the second circuit layer and the pillars are formed on the second circuit layer.

13. The process of claim 11, wherein the photoresist pattern is formed on the first circuit layer and the pillars are formed on the first circuit layer.