Display driving system using single level data transmission with embedded clock signal

• US 8,884,934 B2
• Filed: 09/01/2010
• Issued: 11/11/2014
• Est. Priority Date: 04/05/2010
• Status: Active Grant

• Current Assignee: Silicon Works Co., Ltd.
• Original Assignee: Silicon Works Co., Ltd.
• Inventors: Jeon, Hyun-Kyu, Moon, Yong-Hwan
• Primary Examiner(s): Bost, Dwayne
• Assistant Examiner(s): MICHAUD, ROBERT J
• Application Number:
  US12/873,807
• Publication Number:
  US 20110242066A1
• Time in Patent Office: 1,532 Days
• Field of Search: 345/204, 345/98, 345/99, 345/100
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 5/008 Clock recovery

Abstract

A display driving system using single level data transmission with embedded clock signals. The display driving system is configured to embed a clock signal of the same level between data signals and transmit these signals as a single level signal, wherein a cycle at which clock signals are embedded is controlled and a data format is constructed such that a control data transmission step can be extended over 2 words.

Claims

1. A display driving system comprising:

a timing controller comprising a receiving unit configured to receive data signals, a data processing unit configured to process and output the data signals, a clock generation unit configured to generate clock signals and timing control signals, and a transmission block configured to transmit the data signals, the clock signals, and the timing control signals; and

a panel driving block comprising row driving units configured to sequentially scan gate signals to a display panel, and column driving units configured to receive the data signals transmitted from the transmission block through signal lines and drive the display panel,

wherein the transmission block of the timing controller comprises driving units configured to output transmission data to the column driving units,

wherein the driving units comprise a first driving unit, the column driving units comprise a first column driving unit, the signals lines comprise a first signal line, and the transmission data comprises first transmission data, and wherein the first driving unit is configured to output the first transmission data to the first column driving unit through the first signal line,

wherein the first transmission data comprises clock training data during a clock training data transmission step, control data for controlling the column driving units during a control data transmission step, and RGB data during an RGB data transmission step, the clock training data comprising clocks used by the column driving units to synchronize internally recovered clock signals,

wherein the first transmission data, during the control data transmission step, comprises the clock signals embedded between control data signals, such that amplitudes of the control data signals are the same as amplitudes of the clock signals, and

wherein the first transmission data, during the control data transmission step, comprises a separate TR-bit for each word in the control data, each TR-bit comprising a first data bit in a given word, a value of each TR-bit is low for each continuous word of the control data, the value of the TR-bit is high for a final word of the control data, and the first transmission data transmitted after the final word comprise the RGB data.

2. The display driving system according to claim 1, wherein each clock signal is embedded for each data signal of one RGB pixel among the data signals.

3. The display driving system according to claim 1, wherein each clock signal is embedded for each data signal corresponding to one half of one RGB pixel among the data signals.

4. The display driving system according to claim 1, wherein each clock signal is embedded for each sub-pixel which constitutes the RGB pixel.

5. The display driving system according to claim 1, wherein the timing controller comprises:

the receiving unit configured to receive the data;

the data processing unit configured to temporarily store the received data and output the clock training data, the control data, and the RGB data depending upon a protocol;

the clock generation unit configured to generate the clock signals and the timing control signals; and

the transmission block configured to receive the clock training data, the control data, and the RGB data which are outputted from the data processing unit, serialize these data in response to the clock signals which are outputted from the clock generation unit, and transmit the serialized data,

the transmission block comprising;

a data distribution unit configured to receive the clock training data, the control data, and the RGB data which are outputted from the data processing unit, and distribute data to be transmitted to the column driving units;

parallel-to-serial conversion units configured to convert the distributed data into serial data in response to the clock signals; and

the driving units configured to transmit data outputted from the parallel-to-serial conversion units to the column driving units.

6. The display driving system according to claim 1, wherein,

when the value of a second TR-bit is a low value, the length of the control data transmission step is extended to at least three words, and

when the value of the second TR-bit is a high value, the length of the control data transmission step is not extended to three words and a current word is recognized as the final word in the control data transmission step.

7. The display driving system according to claim 1, wherein the timing controller is configured to additionally serialize a clock signal and a dummy signal in order to indicate transition timing (a rising edge or a falling edge) of the clock signal embedded between the clock training data, the control data, and the RGB data.

8. The display driving system according to claim 7, wherein the dummy signal and the clock signal can be changed in signal width.

9. The display driving system according to claim 1, wherein a first TR-bit distinguishes the clock training data transmission step and the control data transmission step.

10. The display driving system according to claim 9, wherein the first TR-bit is configured by combining one or more data bits.

11. The display driving system according to claim 1,

wherein the column driving units are configured to output LOCK signals(LOCK₁ ˜

LOCK_N-1) in a logic high state sequentially to adjacent column driving units when received clock signals, which are synchronized with the clock training data inputted from the timing controller, are stabilized, and a final column driving unit is configured to transfer a logic high state of a LOCK_N signal to the timing controller, and

wherein the timing controller is configured to end the clock training data transmission step and start transmission of clock-embedded data signals after a predetermined time elapses.

12. The display driving system according to claim 11,

wherein the timing controller is configured to end transmission of the clock training data and sequentially start the control data transmission step and the RGB data transmission step after the predetermined time elapses if the LOCK_N signal received from the final column driving unit in the clock training data transmission step changes to the logic high state, and

wherein the timing controller is configured to transmit again the clock training data until the predetermined time elapses after the LOCK_N signal changes to the logic high state, if the LOCK_N signal changes to a logic low state while transmitting the data from the column driving units.

13. The display driving system according to claim 1, wherein the first column driving unit comprises:

a data receiving section configured to receive clock-embedded data transmitted from the timing controller;

a data latch configured to sequentially store RGB data depending upon control information included in the data received by the data receiving section; and

a digital-to-analog converter configured to drive a panel depending upon values of the RGB data stored in the data latch.

14. The display driving system according to claim 13, wherein the data receiving section comprises:

a clock recovery part configured to recover received clock signals for data sampling; and

a serial-to-parallel conversion part configured to sample and output the control data and the RGB data included in the first transmission data at transition timing (rising edges or falling edges) of the received clock signals.

15. The display driving system according to claim 14,

wherein the data receiving section is configured to recognize the control data transmission step depending upon a first TR-bit transmitted after an embedded clock signal of first control data transmitted after the clock training data transmission step is ended, by using the received clock signals which are stabilized during the clock training data transmission step, and

wherein the data receiving section is configured to recognize the RGB data transmission step from a data word transmitted thereafter, and receive the control data and the RGB data by classifying received signals.

16. The display driving system according to claim 14, wherein the data receiving section is configured to distinguish first control data or final control data depending upon a value of a TR-bit inserted in each control data word when at least one control data word is transmitted during the control data transmission step, and recognize data transmitted thereafter as the RGB data and sample the control data and the RGB data by classifying received signals.

17. The display driving system according to claim 14, wherein the first column driving unit is configured to determine timing at which the RGB data transmission step is ended, by counting a word number of the inputted RGB data on the basis of a predetermined word number of the RGB data, and the RGB data transmission step is ended, in such a manner that whether a next clock training data transmission step is started is determined.

18. The display driving system according to claim 14, wherein the clock recovery part is configured to ease recovery of the received clock signals by using the clock training data transmitted from the transmission block, and to stabilize the recovered received clock signals.

19. The display driving system according to claim 18, wherein the received clock signals comprise multi-phase clock signals which have the same frequency as the clock signals embedded between the clock training data and the RGB data.