Method and apparatus for ESD circuits

• US 8,885,305 B2
• Filed: 04/25/2012
• Issued: 11/11/2014
• Est. Priority Date: 04/25/2012
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Shan, Yi, Prabhu, Manjunatha
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): BROOKS, ANGELA D
• Application Number:
  US13/455,819
• Publication Number:
  US 20130286520A1
• Time in Patent Office: 930 Days
• Field of Search: 361/56, 361/57
• US Class Current: 361/57
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A high performance ESD protection circuit is provided. Embodiments include a circuit having an RC clamp circuit including a first NMOS transistor having a first source, drain, and gate, a current mirror circuit including first and second PMOS transistors having a second and third source, drain, and gate, respectively, and an SCR circuit including a first P+ contact. The first source is coupled to a ground rail, the first drain is coupled to the second drain, second gate, and third gate, the second and third sources are coupled to a power rail, and the third drain is coupled to the first P+ contact, wherein during an ESD event the first NMOS and PMOS transistors turn on to discharge a first current to the ground rail, and the current mirror provides a second current to the first P+ contact for turning on the SCR.

Claims

1. A circuit comprising:

a resistor capacitor (RC) clamp circuit including a first NMOS transistor having a first source, a first drain, and a first gate;

a current mirror circuit including a first PMOS transistor having a second source, a second drain, and a second gate, and a second PMOS transistor having a third source, a third drain, and a third gate; and

a silicon controlled rectifier (SCR) circuit including a first P+ contact,

wherein the first source is coupled to a ground rail, the first drain is coupled to the second drain, to the second gate, and to the third gate, the second source is coupled to a power rail, the third source is coupled to the power rail, and the third drain is coupled to the first P+ contact,

wherein during an ESD event the first NMOS transistor and the first PMOS transistor turn on to discharge a first current to the ground rail, and

wherein the current mirror is utilized to provide a second current to the first P+ contact for turning on the SCR.

2. The circuit according to claim 1, wherein a current ratio of the first current to the second current travelling through the second PMOS transistor is proportional to a size ratio of the first PMOS transistor to the second PMOS transistor.

3. The circuit according to claim 1, wherein the RC clamp circuit further comprises:

a first resistor having a first terminal and a second terminal; and

a first capacitor having a third terminal and a fourth terminal, wherein the first terminal is coupled to the power rail, the second terminal is coupled to the third terminal, and the fourth terminal is coupled to the ground rail.

4. The circuit according to claim 1, wherein the RC clamp circuit further comprises:

a second NMOS transistor having a fourth source, a fourth drain, and a fourth gate; and

a third PMOS transistor having a fifth source, a fifth drain, and a fifth gate,

wherein the fourth source is coupled to the ground rail, the fifth source is coupled to the power rail, the fourth drain is coupled to the fifth drain, the fourth gate and the fifth gate are coupled to the second terminal.

5. The circuit according to claim 1, wherein the RC clamp circuit further comprises:

a third NMOS transistor having a sixth source, a sixth drain, and a sixth gate; and

a fourth PMOS transistor having a seventh source, a seventh drain, and a seventh gate,

wherein the sixth source is coupled to the ground rail, the seventh source is coupled to the power rail, the sixth drain is coupled to the seventh drain, the sixth gate and the seventh gate are coupled to the fourth drain.

6. The circuit according to claim 1, wherein the RC clamp circuit further comprises:

a fourth NMOS transistor having an eighth source, an eighth drain, and an eighth gate; and

a fifth PMOS transistor having a ninth source, a ninth drain, and a ninth gate,

wherein the eighth source is coupled to the ground rail, the ninth source is coupled to the power rail, the eighth drain is coupled to the ninth drain and to the first gate, the eighth gate and the ninth gate are coupled to the sixth drain.

7. The circuit according to claim 1, wherein the SCR circuit further comprises:

an N-well region including,

a first N+ contact and a second P+ contact;

a second resistor having a fifth terminal and a sixth terminal; and

a PNP transistor having a first emitter, a first collector, and a first base,

wherein the first N+ contact and the second P+ contact are coupled to the power rail, and wherein the fifth terminal is coupled to the first N+ contact, the sixth terminal is coupled to the first base, and wherein the first emitter is coupled to the second P+ contact.

8. The circuit according to claim 1, wherein the SCR circuit further comprises:

a P-well region including,

a second N+ contact and a third P+ contact;

a third resistor having a seventh terminal and an eighth terminal; and

an NPN transistor having a second emitter, a second collector, and a second base,

wherein the second N+ contact and the third P+ contact are coupled to the ground rail, and

wherein the seventh terminal is coupled to the third P+ contact, and

wherein the eighth terminal is coupled to the second base, to the first P+ contact, and to the first collector, and

wherein the second emitter is coupled to the second N+ contact and second collector is connected to the first base.

9. The circuit according to claim 7, further comprising:

an input/output (I/O) pad; and

a diode having an anode terminal and a cathode terminal,

wherein the anode terminal is coupled to the I/O pad, to the first N+ contact and to the second P+ contact, and wherein the cathode terminal is coupled to the power rail.

10. A circuit comprising:

a resistor capacitor (RC) clamp circuit including a first PMOS transistor having a first source, a first drain, and a first gate;

a silicon controlled rectifier (SCR) circuit including a first N+ contact; and

a current mirror circuit including a first NMOS transistor having a second source, a second drain, a second gate, and a second NMOS transistor having a third source, a third drain, and a third gate,

wherein the first source is coupled to a power rail, the first drain is coupled to the second drain, the second gate, and the third gate, the second source is coupled to a ground rail, the third source is coupled to the ground rail, and the third drain is coupled to the first N+ contact, and

wherein during an ESD event the first NMOS transistor and the first PMOS transistor turn on to discharge a first current to the ground rail, and

wherein the current mirror is utilized to provide a second current to the SCR for turning on the SCR.

11. The circuit according to claim 10, wherein a current ratio of the first current to the second current travelling through the second NMOS transistor is proportional to a size ratio of the first NMOS transistor to the second NMOS transistor.

12. The circuit according to claim 10, wherein the RC clamp circuit further comprises:

a first resistor having a first terminal and a second terminal; and

a first capacitor having a third terminal and a fourth terminal,

wherein the first terminal is coupled to the power rail, the second terminal is coupled to the third terminal, and the fourth terminal is coupled to the ground rail.

13. The circuit according to claim 10, wherein the RC clamp circuit further comprises:

a second PMOS transistor having a fourth source, a fourth drain, and a fourth gate; and

a third NMOS transistor having a fifth source, a fifth drain, and a fifth gate,

wherein the fourth source is coupled to the power rail, the fourth drain is coupled to the fifth drain, the fourth gate and the fifth gate are coupled to the second terminal, and the fifth source is coupled to the ground rail.

14. The circuit according to claim 10, wherein the RC clamp circuit further comprises:

a third PMOS transistor having a sixth source, a sixth drain, and a sixth gate; and

a fourth NMOS transistor having a seventh source, a seventh drain, and a seventh gate,

wherein the sixth source is coupled to the power rail, the sixth drain is coupled to the seventh drain and to the first gate, the sixth gate is coupled to the seventh gate and to the fourth drain, and the seventh source is coupled to the ground rail.

15. The circuit according to claim 10, wherein the SCR circuit further comprises:

an N-well region including,

a first P+ contact and a second N+ contact;

a second resistor having a fifth terminal and a sixth terminal; and

a PNP transistor having a first emitter, a first collector, and a first base,

wherein the first P+ contact and the second N+ contact are coupled to the power rail, and

wherein the fifth terminal is coupled to the second N+ contact, the sixth terminal is coupled to the first base and the first N+ contact, and

wherein the first emitter is coupled to the first P+ contact.

16. The circuit according to claim 10, wherein the SCR circuit further comprises:

a P-well region including,

a second P+ contact and a third N+ contact;

a third resistor having a seventh terminal and an eighth terminal; and

an NPN transistor having a second emitter, a second collector, and a second base,

wherein the second P+ contact and the third N+ contact are coupled to the ground rail, and

wherein the seventh terminal is coupled to the second P+ contact, the eighth terminal is coupled to the second base and to the first collector, and

wherein the second emitter is coupled to the third N+ contact and the second collector is connected to the first base.

17. The circuit according to claim 15, further comprising:

an input/output (I/O) pad; and

a diode having an anode terminal and a cathode terminal,

wherein the anode terminal is coupled to the I/O pad, to the first P+ contact and to the second N+ contact, and the cathode terminal is coupled to the power rail.

18. A method comprising:

providing a resistor capacitor (RC) clamp circuit including a first NMOS transistor having a first source, a first drain, and a first gate;

providing a current mirror circuit including a first PMOS transistor having a second source, a second drain, a second gate, and a second PMOS transistor having a third source, a third drain, and a third gate;

providing a silicon controlled rectifier (SCR) circuit including a first P+ contact, a second P+ contact and a first N+ contact;

coupling the first source to a ground rail, the first drain is coupled to the second drain, the second gate, and the third gate, the second source is coupled to a power rail, the third source is coupled to the power rail, and the third drain is coupled to the first P+ contact,

wherein during an ESD event the first NMOS transistor and the first PMOS transistor turn on to discharge a first current to the ground rail; and

providing a second current to the first P+ contact for turning on the SCR.

19. The method according to claim 18, wherein a current ratio of the first current to the second current travelling through the second PMOS transistor is proportional to a size ratio of the first PMOS transistor to the second PMOS transistor.

20. The method according to claim 18, further comprising:

providing an input/output (I/O) pad;

providing a diode having an anode terminal and a cathode terminal; and

coupling the anode terminal to the I/O pad, to the first N+ contact and to the second P+ contact, and wherein the cathode terminal is coupled to the power rail.