Method and apparatus for ESD circuits
First Claim
1. A circuit comprising:
- a resistor capacitor (RC) clamp circuit including a first NMOS transistor having a first source, a first drain, and a first gate;
a current mirror circuit including a first PMOS transistor having a second source, a second drain, and a second gate, and a second PMOS transistor having a third source, a third drain, and a third gate; and
a silicon controlled rectifier (SCR) circuit including a first P+ contact,wherein the first source is coupled to a ground rail, the first drain is coupled to the second drain, to the second gate, and to the third gate, the second source is coupled to a power rail, the third source is coupled to the power rail, and the third drain is coupled to the first P+ contact,wherein during an ESD event the first NMOS transistor and the first PMOS transistor turn on to discharge a first current to the ground rail, andwherein the current mirror is utilized to provide a second current to the first P+ contact for turning on the SCR.
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Accused Products
Abstract
A high performance ESD protection circuit is provided. Embodiments include a circuit having an RC clamp circuit including a first NMOS transistor having a first source, drain, and gate, a current mirror circuit including first and second PMOS transistors having a second and third source, drain, and gate, respectively, and an SCR circuit including a first P+ contact. The first source is coupled to a ground rail, the first drain is coupled to the second drain, second gate, and third gate, the second and third sources are coupled to a power rail, and the third drain is coupled to the first P+ contact, wherein during an ESD event the first NMOS and PMOS transistors turn on to discharge a first current to the ground rail, and the current mirror provides a second current to the first P+ contact for turning on the SCR.
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Citations
20 Claims
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1. A circuit comprising:
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a resistor capacitor (RC) clamp circuit including a first NMOS transistor having a first source, a first drain, and a first gate; a current mirror circuit including a first PMOS transistor having a second source, a second drain, and a second gate, and a second PMOS transistor having a third source, a third drain, and a third gate; and a silicon controlled rectifier (SCR) circuit including a first P+ contact, wherein the first source is coupled to a ground rail, the first drain is coupled to the second drain, to the second gate, and to the third gate, the second source is coupled to a power rail, the third source is coupled to the power rail, and the third drain is coupled to the first P+ contact, wherein during an ESD event the first NMOS transistor and the first PMOS transistor turn on to discharge a first current to the ground rail, and wherein the current mirror is utilized to provide a second current to the first P+ contact for turning on the SCR. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A circuit comprising:
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a resistor capacitor (RC) clamp circuit including a first PMOS transistor having a first source, a first drain, and a first gate; a silicon controlled rectifier (SCR) circuit including a first N+ contact; and a current mirror circuit including a first NMOS transistor having a second source, a second drain, a second gate, and a second NMOS transistor having a third source, a third drain, and a third gate, wherein the first source is coupled to a power rail, the first drain is coupled to the second drain, the second gate, and the third gate, the second source is coupled to a ground rail, the third source is coupled to the ground rail, and the third drain is coupled to the first N+ contact, and wherein during an ESD event the first NMOS transistor and the first PMOS transistor turn on to discharge a first current to the ground rail, and wherein the current mirror is utilized to provide a second current to the SCR for turning on the SCR. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method comprising:
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providing a resistor capacitor (RC) clamp circuit including a first NMOS transistor having a first source, a first drain, and a first gate; providing a current mirror circuit including a first PMOS transistor having a second source, a second drain, a second gate, and a second PMOS transistor having a third source, a third drain, and a third gate; providing a silicon controlled rectifier (SCR) circuit including a first P+ contact, a second P+ contact and a first N+ contact; coupling the first source to a ground rail, the first drain is coupled to the second drain, the second gate, and the third gate, the second source is coupled to a power rail, the third source is coupled to the power rail, and the third drain is coupled to the first P+ contact, wherein during an ESD event the first NMOS transistor and the first PMOS transistor turn on to discharge a first current to the ground rail; and providing a second current to the first P+ contact for turning on the SCR. - View Dependent Claims (19, 20)
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Specification