Mask-programmed read-only memory with reserved space

• US 8,885,384 B2
• Filed: 03/18/2013
• Issued: 11/11/2014
• Est. Priority Date: 01/11/2007
• Status: Expired due to Fees

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): King, Douglas
• Application Number:
  US13/846,928
• Publication Number:
  US 20130227204A1
• Time in Patent Office: 603 Days
• Field of Search: 365/94, 365/100, 365/102, 365/103, 365/105, 257/390, 257/E33.012, 69/94, 691/00, 691/02, 691/03, 691/05
• US Class Current: 365/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 17/10 in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
• CPC Class Codes: G11C 17/146 Write once memory, i.e. allowing changing of memory content by writing additional bits
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/38 Doping programmed, e.g. mask ROM

Abstract

The present invention discloses a mask-ROM with reserved space (mask-ROM_RS). For small content revision, the present invention salvages the original data-mask by writing the data-pattern of new content into a reserved mask-region which originally has no data-pattern.

Claims

1. A mask-programmed read-only memory (mask- ROM) family, comprising:

a first mask-ROM die comprising at least a first memory array;

a second mask-ROM die comprising at least a second memory array;

wherein said first and second memory arrays are same except for a reserved portion, said reserved portion comprising a same plurality of mask-ROM cells in said first and second memory arrays, wherein all mask-ROM cells in the reserved portion of said first memory array have a same structure, and the mask-ROM cells in the reserved portion of said second memory array have at least two structures.

2. The mask-ROM family according to claim 1, wherein all mask-ROM cells in the reserved portion of said first memory array comprise a data layer.

3. The mask-ROM family according to claim 1, wherein all mask-ROM cells in the reserved portion of said first memory array comprise no data layer.

4. The mask-ROM family according to claim 1, wherein at least selected mask-ROM cells in the reserved portion of said second memory array comprise a data layer.

5. The mask-ROM family according to claim 1, wherein at least selected mask-ROM cells in the reserved portion of said second memory array comprise no data layer.

6. The mask-ROM family according to claim 1, wherein the total number of the mask-ROM cells in the reserved portion is more than 10% of the total number of the mask-ROM cells in said first memory array.

7. The mask-ROM family according to claim 1, wherein the total number of the mask-ROM cells in the reserved portion is more than 10% of the total number of the mask-ROM cells in said second memory array.

8. The mask-ROM family according to claim 1, wherein each of said first and second mask-ROM dice further comprises an address translator.

9. The mask-ROM family according to claim 8, wherein said address translator comprises a non-volatile memory for storing an address-mapping table.

10. The mask-ROM family according to claim 9, wherein said non-volatile memory is a re-writable memory.

11. The mask-ROM family according to claim 10, wherein said re-writable memory is a flash memory.