Compression of content entries in storage for replacing faulty memory cells

• US 8,885,426 B1
• Filed: 02/27/2013
• Issued: 11/11/2014
• Est. Priority Date: 06/25/2012
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Inphi Corporation
• Inventors: Burstein, Andrew, Saxena, Nirmal, Villagomez, Javier
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/778,531
• Time in Patent Office: 622 Days
• Field of Search: 365/201, 365/149, 365/200
• US Class Current: 365/201
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: G11C 29/802 by encoding redundancy signals
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A method of manufacturing a dynamic random access memory device is provided. The method includes testing a DRAM device using a testing process. The method includes identifying, under control by a computing device, a plurality of bad memory cells from the DRAM device and determining a list of addresses associated with the plurality of bad memory cells. The method includes sorting the list of addresses in either ascending or descending order and subjecting the information from the sorted list of address to a compression process, under control by the computing device, to provide a compressed format including a first content entry in the sorted list and a series of off-set values as provided by a recurrence relationship. The method also stores the compressed format into a non-volatile memory.

Claims

1. A method of manufacturing a dynamic random access memory device, the method comprising:

testing a DRAM device using a testing process, the DRAM device comprising a plurality of memory arrays, each of the plurality of memory arrays comprising a plurality of memory cells;

identifying, under control by a computing device, a plurality of bad memory cells from the DRAM device;

determining a list of addresses associated with the plurality of bad memory cells from the DRAM device;

sorting the list of address in either ascending or descending order;

subjecting the information from the sorted list of addresses to a compression process, under control by the computing device, to provide a compressed format including a first content entry in the sorted list and a series of off-set values as provided by a recurrence relationship; and

storing the compressed format into a non-volatile memory.

2. The method of claim 1 wherein the first content entry is uncompressed, and wherein the series of off-set values are Delta Encoded Entries.

3. The method of claim 1 further comprising initializing an interface integrated circuit device coupled to the DRAM device to initialize a decompression process of the compressed format in the non-volatile memory;

and loading the list of addresses into an address match table.

4. The method of claim 1 further comprising determining a quanta size for the compression process.

5. The method of claim 4 further comprising successively storing each of the off-set values within a size of a quanta according to the quanta size, and using multiple quanta if the off-set value is larger than the size of the quanta.

6. The method of claim 1 further comprising decompressing the compressed format into an address match table during an in-field repair process.

7. The method of claim 1 wherein each of the plurality of bad memory cells is a faulty or weak memory cell.

8. The method of claim 1 further comprising

subjecting the DRAM device to an in-field repair process;

determining an updated list of addresses associated with the plurality of bad memory cells of the DRAM device;

subjecting the information from the updated list of addresses to a compression process, under control by the computing device, to provide an updated compressed format including an updated first content entry in the updated list and a series of updated off-set values as provided by a recurrence relationship; and

storing the updated compressed format into the non-volatile memory.

9. A method of manufacturing a dynamic random access memory cell, the method comprising:

testing a DRAM device using a testing process, the DRAM device comprising a plurality of memory arrays, each of the plurality of memory arrays comprising a plurality of memory cells;

identifying, under control by a computing device, a plurality of bad memory cells from the DRAM device;

determining a list of addresses associated with the plurality of bad memory cells from the DRAM device;

sorting the list of addresses in either an ascending or a descending order;

subjecting the information from the sorted list of addresses to a compression process, under control by the computing device, to provide a compressed format including a first content entry in the sorted list and a series of off-set values as provided by a recurrence relationship;

storing the compressed format into a non-volatile memory;

initiating a process to decompress the compressed format; and

loading the list of addresses in an address match table for use in replacing bad memory cells with spare memory cells.

10. The method of claim 9 wherein the first content entry is uncompressed;

and wherein the series of off-set values are Delta Encoded Entries.

11. The method of claim 9 further comprising determining a quanta size for the compression process.

12. The method of claim 11 further comprising successively storing each of the off-set values within a size of a quanta according to the quanta size;

and using multiple quanta if the off-set value is larger than the size of the quanta.

13. The method of claim 9 wherein the decompressing of the compressed format is during an in-field repair process.

14. The method of claim 9 wherein each of the bad memory cells is faulty or weak memory cell.

15. The method of claim 9 further comprising

subjecting the DRAM device to an in-field repair process;

determining an updated list of addresses associated with the plurality of bad memory cells of the DRAM device;

subjecting the information from the updated list of addresses to a compression process, under control by the computing device, to provide an updated compressed format including an updated first content entry in the updated list and a series of updated off-set values as provided by a recurrence relationship; and

storing the updated compressed format into the non-volatile memory.

16. A module apparatus, the apparatus comprising:

a non-volatile memory device comprising an address listing of a plurality of bad memory cells of a memory device, the address listing being configured as a compressed format including a first content entry in a sorted list of the address listing and a series of off-set values as provided by a recurrence relationship; and

an address match table configured for receiving the address listing from the non-volatile memory device in an uncompressed format from the compressed format.

17. The device of claim 16 wherein each of the off-set values is within a size of a quanta according to a quanta size;

and wherein each of the off-set values is within multiple quanta if the off-set value is larger than the quanta size.

18. The device of claim 16 wherein each of the bad memory cells is a faulty or weak memory cell.

19. The device of claim 16 wherein the first content entry is uncompressed;

and wherein the series of off-set values are Delta Encoded Entries.

20. The device of claim 19 wherein each of the Delta Encoded Entries is provided in at least one quanta.

21. The device of claim 16 wherein the module apparatus comprises a monolithically integrated non-volatile memory and the address match table.