Storage device and driving method thereof

• US 8,885,437 B2
• Filed: 11/30/2012
• Issued: 11/11/2014
• Est. Priority Date: 12/02/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsuzaki, Takanori
• Primary Examiner(s): Le, Vu
• Application Number:
  US13/690,483
• Publication Number:
  US 20130141961A1
• Time in Patent Office: 711 Days
• Field of Search: 365/230.03, 365/189.09, 365/189.011
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a highly integrated storage device which can operate at high speed and a driving method thereof. The storage device includes two storage portions, two precharge switches, and one sense amplifier. In each of the storage portions, storage elements are arranged in a matrix. In each of the storage elements, a node electrically connected to a source or a drain of a transistor whose off-state current is small is a memory storing portion. A page buffer circuit is unnecessary; thus, high-speed operation is possible and high integration is achieved.

Claims

1. A driving method of a storage device comprising a first memory cell and a second memory cell, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a first bit line, wherein the other of the source and the drain of the first transistor is electrically connected to a first source line, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the first bit line, wherein a first electrode of the first capacitor is electrically connected to the gate of the first transistor, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein one of a source and a drain of the third transistor is electrically connected to a second bit line, wherein the other of the source and the drain of the third transistor is electrically connected to a second source line, wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second bit line, and wherein a first electrode of the second capacitor is electrically connected to the gate of the third transistor, the driving method comprising the steps of:

supplying a first potential to the first source line;

supplying a second potential to the first bit line;

electrically isolating the first bit line after supplying the second potential to the first bit line;

changing a potential of a second electrode of the first capacitor from a third potential to a fourth potential so that the first potential or the second potential is supplied to the first bit line;

supplying a fifth potential lower than the second potential to the second bit line;

supplying a sixth potential or a seventh potential to the first bit line in accordance with the potential of the first bit line; and

turning on a switch provided between the first bit line and an input-output line to read out data of the first bit line.

2. The driving method according to claim 1,

wherein the sixth potential is higher than the second potential, and

wherein the seventh potential is equal to or lower than the first potential.

3. The driving method according to claim 1,

wherein the first potential, the fourth potential, and the seventh potential are equal to one another,

wherein the third potential is equal to the sixth potential, and

wherein the second potential is higher than the first potential and lower than the third potential.

4. The driving method according to claim 3,

wherein the first potential is a ground potential, and

wherein the third potential is a power supply potential.

5. The driving method according to claim 1,

wherein the second transistor comprises a channel formation region comprising an oxide semiconductor.

6. The driving method according to claim 5,

wherein an off-state current of the second transistor is 100 zA or less at 25°

C.

7. A driving method of a storage device comprising a first memory cell and a sense amplifier, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a first bit line, wherein the other of the source and the drain of the first transistor is electrically connected to a first source line, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the first bit line, wherein a first electrode of the first capacitor is electrically connected to the gate of the first transistor, and wherein the first bit line is electrically connected to the sense amplifier, the driving method comprising the steps of:

supplying a first potential to the first bit line;

electrically isolating the first bit line after supplying the first potential to the first bit line;

changing a potential of a second electrode of the first capacitor so that a signal is output to the first bit line in accordance with a voltage held in the first capacitor;

amplifying the signal by the sense amplifier; and

reading out the amplified signal through a switch from the first bit line to an input-output line by turning on the switch.

8. The driving method according to claim 7, wherein the storage device further comprises a second memory cell, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein one of a source and a drain of the third transistor is electrically connected to a second bit line, wherein the other of the source and the drain of the third transistor is electrically connected to a second source line, wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second bit line, wherein a first electrode of the second capacitor is electrically connected to the gate of the third transistor, and wherein the second bit line is electrically connected to the sense amplifier, the driving method further comprising the steps of:

supplying a second potential to the second bit line before amplifying the signal by the sense amplifier.

9. The driving method according to claim 7,

wherein the second transistor comprises a channel formation region comprising an oxide semiconductor.

10. The driving method according to claim 9,

wherein an off-state current of the second transistor is 100 zA or less at 25°

C.

11. A driving method of a storage device comprising a first memory cell and a second memory cell, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a first bit line, wherein the other of the source and the drain of the first transistor is electrically connected to a first source line, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the first bit line, wherein a first electrode of the first capacitor is electrically connected to the gate of the first transistor, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein one of a source and a drain of the third transistor is electrically connected to a second bit line, wherein the other of the source and the drain of the third transistor is electrically connected to a second source line, wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second bit line, and wherein a first electrode of the second capacitor is electrically connected to the gate of the third transistor, the driving method comprising the steps of:

supplying a first potential to the first source line;

supplying a second potential to the first bit line;

electrically isolating the first bit line after supplying the second potential to the first bit line;

changing a potential of a second electrode of the first capacitor from a third potential to a fourth potential so that the first potential or the second potential is supplied to the first bit line;

supplying a fifth potential lower than the second potential to the second bit line;

turning on a switch provided between the first bit line and an input-output line so that a sixth potential or a seventh potential is supplied to the first bit line, whereby data is written to the first memory cell; and

turning off the second transistor after turning on the switch.

12. The driving method according to claim 11,

wherein the sixth potential is higher than the second potential, and

wherein the seventh potential is equal to or lower than the first potential.

13. The driving method according to claim 11,

wherein the first potential, the fourth potential, and the seventh potential are equal to one another,

wherein the third potential is equal to the sixth potential, and

wherein the second potential is higher than the first potential and lower than the third potential.

14. The driving method according to claim 13,

wherein the first potential is a ground potential, and

wherein the third potential is a power supply potential.

15. The driving method according to claim 11,

wherein the second transistor comprises a channel formation region comprising an oxide semiconductor.

16. The driving method according to claim 15,

wherein an off-state current of the second transistor is 100 zA or less at 25°

C.

17. A driving method of a storage device comprising a first memory cell, a second memory cell, and a sense amplifier, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein one of a source and a drain of the first transistor is electrically connected to a first bit line, wherein the other of the source and the drain of the first transistor is electrically connected to a first source line, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the first bit line, wherein a first electrode of the first capacitor is electrically connected to the gate of the first transistor, wherein the first bit line is electrically connected to the sense amplifier, wherein the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein one of a source and a drain of the third transistor is electrically connected to a second bit line, wherein the other of the source and the drain of the third transistor is electrically connected to a second source line, wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second bit line, wherein a first electrode of the second capacitor is electrically connected to the gate of the third transistor, and wherein the second bit line is electrically connected to the sense amplifier, the driving method comprising the steps of:

turning on the second transistor;

inputting a first signal through a first switch from a first input-output line to the first bit line by turning on the first switch;

inputting a second signal through a second switch from a second input-output line to the second bit line by turning on the second switch; and

turning off the second transistor after inputting the first signal and the second signal,

wherein the first signal and the second signal are amplified by the sense amplifier.

18. The driving method according to claim 17,

wherein the second transistor comprises a channel formation region comprising an oxide semiconductor.

19. The driving method according to claim 18,

wherein an off-state current of the second transistor is 100 zA or less at 25°

C.

20. A storage device comprising:

a first storage portion;

a second storage portion;

a first switch,

a second switch,

a first driver circuit, and

a second driver circuit,

wherein in each of the first storage portion and the second storage portion, a plurality of storage elements is arranged in a matrix,

wherein the first storage portion is electrically connected to the first switch,

wherein the second storage portion is electrically connected to the second switch,

wherein the first driver circuit comprises is two precharge switches and one sense amplifier,

wherein in each of the plurality of storage elements, a node electrically connected to a source or a drain of a first transistor is a memory storing portion, and

wherein the first transistor comprises a first channel formation region comprising an oxide semiconductor.

21. The storage device according to claim 20,

wherein an off-state current of the first transistor is 100 zA or less at 25°

C.

22. The storage device according to claim 20,

wherein each of the plurality of storage elements comprises a second transistor,

wherein a gate of the second transistor is electrically connected to the node, and

wherein the second transistor comprises a second channel formation region comprising single crystal silicon.

23. A storage device comprising:

a first memory cell comprising;

a first transistor;

a second transistor; and

a first capacitor;

a second memory cell comprising;

a third transistor;

a fourth transistor; and

a second capacitor; and

a sense amplifier comprising;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a first bit line,

wherein the other of the source and the drain of the first transistor is electrically connected to a first source line,

wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the first bit line,

wherein a first electrode of the first capacitor is electrically connected to the gate of the first transistor,

wherein the first bit line is electrically connected to the sense amplifier,

wherein one of a source and a drain of the third transistor is electrically connected to a second bit line,

wherein the other of the source and the drain of the third transistor is electrically connected to a second source line,

wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the second bit line,

wherein a first electrode of the second capacitor is electrically connected to the gate of the third transistor,

wherein the second bit line is electrically connected to the sense amplifier,

wherein one of a source and a drain of the fifth transistor is electrically connected to the first bit line,

wherein a gate of the fifth transistor is electrically connected to the second bit line,

wherein one of a source and a drain of the sixth transistor is electrically connected to the first bit line,

wherein a gate of the sixth transistor is electrically connected to the second bit line,

wherein one of a source and a drain of the seventh transistor is electrically connected to the second bit line,

wherein a gate of the seventh transistor is electrically connected to the first bit line,

wherein one of a source and a drain of the eighth transistor is electrically connected to the second bit line, and

wherein a gate of the eighth transistor is electrically connected to the first bit line.

24. The storage device according to claim 23,

wherein the second transistor comprises a channel formation region comprising an oxide semiconductor.

25. The storage device according to claim 24,

wherein an off-state current of the second transistor is 100 zA or less at 25°

C.