Data block processor in a mobile DTV system with diversity

• US 8,885,663 B2
• Filed: 12/03/2009
• Issued: 11/11/2014
• Est. Priority Date: 12/03/2009
• Status: Expired due to Fees

• Current Assignee: Magnolia Licensing LLC (IP Edge LLC)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Markman, Ivonete
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Belur, Deepa
• Application Number:
  US13/511,682
• Publication Number:
  US 20120275469A1
• Time in Patent Office: 1,804 Days
• Field of Search: 370/464
• US Class Current: 370/464
• CPC Class Codes: H03M 13/2963 Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
• CPC Class Codes: H03M 13/6331 Error control coding in combination with equalisation
• CPC Class Codes: H03M 13/6538 ATSC VBS systems
• CPC Class Codes: H03M 13/658 Scaling by multiplication or division
• CPC Class Codes: H03M 3/3283 the dither being in the time domain
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04N 21/2383 Channel coding or modulation of digital bit-stream, e.g. QPSK modulation arrangements for detecting or preventing errors in the information received by adapting the channel coding H04L1/0009; analogue front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/631 Multimode Transmission, e.g. transmitting basic layers and enhancement layers of the content over different transmission paths or transmitting with different error corrections, different keys or with different transmission protocols

Abstract

An apparatus for processing a first and a second stream of digital data includes a stagger multiplexer and a stagger demultiplexer. Each stream of digital data includes data blocks. The stagger multiplexer processes the first and the second streams of digital data concurrently to output a combined stream of digital data. The stagger demultiplexer processes the combined stream of digital data to output a first and a second stream of extrinsic digital data.

Claims

1. An apparatus for processing a first and a second stream of digital data, each stream of digital data including data blocks, the apparatus comprising:

a stagger multiplexer that processes the first and the second streams of digital data concurrently to output a combined stream of digital data; and

a stagger demultiplexer that processes the combined stream of digital data to output a first and a second stream of extrinsic digital data, wherein data blocks of the first stream of extrinsic digital data include alternating groups of information blocks and zero blocks and data blocks of the second stream of extrinsic digital data include alternating groups of parity blocks and zero blocks.

2. The apparatus of claim 1, wherein the stagger multiplexer comprises:

a first memory that processes the first stream of digital data; and

a second memory that processes the second stream of digital data;

wherein each memory includes M memory blocks, each memory block including N words, each word including B bits and the first and second streams of digital data are processed concurrently.

3. The apparatus of claim 2, wherein the first and the second streams of digital data include groups of 2*M data blocks and the combined stream of digital data includes groups of 2*M data blocks.

4. The apparatus of claim 3, wherein the first memory writes data blocks received from the first stream of digital data to memory blocks and the second memory writes data blocks received from the second stream of digital data to memory blocks concurrently, each data block written at a rate of one data block per time interval T.

5. The apparatus of claim 4, wherein each of the first memory and second memory writes data blocks to their respective memory blocks by continuously rotating through their respective M memory blocks.

6. The apparatus of claim 4, wherein the combined stream of digital data is generated by alternately extracting data blocks from the memory blocks of the first memory and the memory blocks of the second memory, starting with the first memory.

7. The apparatus of claim 6, wherein each of the first memory and second memory extracts data blocks from their respective memory blocks by continuously rotating through their respective M memory blocks.

8. The apparatus of claim 6, wherein the extracting of a first data block from the first memory is performed after a first word of a first data block is written to the first memory.

9. The apparatus of claim 1, wherein the stagger demultiplexer comprises:

a first memory and a second memory that process the combined stream of digital data;

wherein each memory includes M memory blocks, each memory block including N words, each word including B bits and the first and second output streams of digital data are processed concurrently.

10. The apparatus of claim 9, wherein the first and second memory alternately write data blocks received from the combined stream to their respective memory blocks, starting with the first memory, the data blocks being written at a rate of one data block to the first memory and one data block to the second memory per time period T.

11. The apparatus of claim 10, wherein each of the first memory and second memory writes data blocks to their respective memory blocks by continuously rotating through their respective M memory blocks.

12. The apparatus of claim 10, wherein the first stream of extrinsic digital data and the second stream of extrinsic digital data are generated concurrently, by extracting data blocks from the memory blocks of the first memory to generate the first stream of extrinsic digital data and extracting data blocks from the memory blocks of the second memory to generate the second stream of extrinsic digital data.

13. The apparatus of claim 12, wherein each of the first memory and second memory extracts data blocks from their respective memory blocks by continuously rotating through their respective M memory blocks.

14. The apparatus of claim 12, wherein the extracting of a first data block from the first memory and the extracting of a first data block from the second memory are performed after the respective Mth memory blocks of the first and second memory are written to.