Methods and apparatus for signaling on a differential link

• US 8,885,735 B2
• Filed: 12/24/2012
• Issued: 11/11/2014
• Est. Priority Date: 03/14/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Schoenborn, Theodore
• Primary Examiner(s): Corrielus, Jean B
• Application Number:
  US13/726,476
• Publication Number:
  US 20130114747A1
• Time in Patent Office: 687 Days
• Field of Search: 375259-260, 375/316, 340/10.33, 327/65
• US Class Current: 375/259
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

A receiver is to enter a reduced power state and identify a differential signal transmitted, by a transmitter, over a differential, point-to-point serial data link. The signal is interpreted as a wake signal and can be used to transition at least a portion of the receiver from the reduced power state to a normal power state.

Claims

1. An apparatus comprising:

a receiver comprising logic, when executed, to;

enter a reduced power state;

identify that a differential signal, transmitted in-band with a differential point-to-point serial data link by a transmitter, comprises a predetermined differential voltage condition for at least a predetermined length of time;

interpret the signal as a wake signal based at least in part on the predetermined differential voltage condition for at least the predetermined length of time; and

transition at least one particular component from the reduced power state to a normal power state based at least in part on the wake signal.

2. The apparatus of claim 1, wherein the receiver is further configured to identify an idle condition on the data link in excess of the predetermined length of time and the receiver is to enter the reduced power state based on the identification of the idle condition.

3. The apparatus of claim 2, wherein the idle condition is to be interpreted as a different in-band signal to enter the reduced power state.

4. The apparatus of claim 1, wherein the receiver does not receive data when in the reduced power state.

5. The apparatus of claim 1, wherein the reduced power state is a non-zero power state.

6. The apparatus of claim 1, wherein the signal comprises a direct current (DC) signal.

7. The apparatus of claim 6, wherein the signal comprises a pulse.

8. The apparatus of claim 1, wherein the signal comprises an alternating current (AC) switching signal.

9. The apparatus of claim 8, wherein the signal comprises dummy data.

10. The apparatus of claim 1, wherein interpreting the signal as a wake signal includes identifying a particular one of a plurality of components included in the receiver to awake based on information included in the differential signal.

11. An apparatus comprising:

a transmitter to;

transmit an in-band power management signal to a receiver over a differential point-to-point serial data link, wherein the signal comprises a predetermined differential voltage condition for at least a predetermined length of time to be interpreted as a wake signal to prompt the receiver to transition from a reduced power state to a normal power state; and

transmit data to the receiver over the data link while the receiver is in the normal power state.

12. The apparatus of claim 11, wherein the signal is to comprise a direct current (DC) signal.

13. The apparatus of claim 11, wherein the link comprises at least two lines and the transmitter is to generate the signal by applying a voltage to a particular one of the at least two lines.

14. The apparatus of claim 11, wherein the signal is to comprise an alternating current (AC) switching signal.

15. An apparatus comprising:

a first receiver to use a first differential point-to-point serial data link including at least two lines, wherein the first data link is included in a pair of differential, point-to-point serial data links, and the first receiver is to;

identify an idle condition on the first data link in excess of a predetermined length of time;

enter a reduced power state responsive to identifying the idle condition;

identify that a differential signal, transmitted in-band with the first data link including at least two lines, comprises a predetermined differential voltage condition for at least the predetermined length of time;

interpret the signal as representing an exit from the idle condition based at least in part on the predetermined differential voltage condition for at least the predetermined length of time; and

transition at least one particular component from the reduced power state to a normal power state responsive to the signal.

16. The apparatus of claim 15, further comprising a transmitter to use a second data link in the pair of data links, wherein the transmitter is to:

transmit wake signals over the second data link to prompt a second receiver to transition from a reduced power state to a normal power state.

17. A system comprising:

a data link comprising a differential, point-to-point serial data link;

a first device;

a second device communicatively coupled to the first device using the data link, the second device configured to;

identify an idle condition on the data link;

enter a reduced power state based at least in part on the idle condition;

receive a differential signal transmitted in-band with the data link from the first device;

identify that the signal comprises a predetermined differential voltage condition for at least a predetermined length of time;

interpret the signal as a wake signal based at least in part on the predetermined differential voltage condition for at least the predetermined length of time; and

transition at least one particular component from the reduced power state to a normal power state based at least in part on the wake signal.

18. The system of claim 17, wherein the data link permits data transfer between the first and second devices in excess of 2.5 Gbit per second.

19. The system of claim 17, wherein the data link is a first data link, the system further comprising a second differential point-to-point serial data link communicatively coupling the first and second devices.

20. A method comprising:

entering a reduced power state;

identifying, at a hardware receiver, that a differential signal transmitted in-band with a differential point-to-point serial data link comprises a predetermined differential voltage condition for at least a predetermined length of time;

interpreting the signal as a wake signal based at least in part on the predetermined differential voltage condition for at least the predetermined length of time; and

transitioning at least one particular component from the reduced power state to a normal power state based at least in part on the wake signal.

21. The method of claim 20, further comprising:

identifying an idle condition on the data link in excess of the predetermined length of time; and

entering the reduced power state based on the identification of the idle condition.

22. The method of claim 21, wherein the idle condition is interpreted as a different in-band signal to enter the reduced power state.

23. The method of claim 20, wherein the receiver does not receive data when in the reduced power state.

24. The method of claim 20, further comprising communicating over the link while in the normal power state.