Deterministic finite automata graph traversal with nodal bit mapping
First Claim
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1. A computer implemented method comprising:
- given a current node and an arc pointing from the current node to a next node, analyzing arcs in a graph to determine which of the arcs are valid arcs pointing from the next node;
constructing arc configuration information associated with the arc pointing from the current node to the next node, the arc configuration information representing the valid arcs pointing from the next node; and
storing the arc configuration information representing the valid arcs pointing from the next node in the arc pointing from the current node to the next node to enable the arc configuration information to be evaluated and the valid arcs pointing from the next node to be identified from the evaluation of the arc configuration information without the next node being read.
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Abstract
An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc may also include a nodal bit map including structural information of a node to which the valid arc points to. A walker process may utilize the nodal bit map to determine if a memory access is necessary. The nodal bit map reduces the number of external memory access and therefore reduces system run time.
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Citations
19 Claims
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1. A computer implemented method comprising:
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given a current node and an arc pointing from the current node to a next node, analyzing arcs in a graph to determine which of the arcs are valid arcs pointing from the next node; constructing arc configuration information associated with the arc pointing from the current node to the next node, the arc configuration information representing the valid arcs pointing from the next node; and storing the arc configuration information representing the valid arcs pointing from the next node in the arc pointing from the current node to the next node to enable the arc configuration information to be evaluated and the valid arcs pointing from the next node to be identified from the evaluation of the arc configuration information without the next node being read. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system for locating an expression in a searchable deterministic finite automata-based graph, the system comprising:
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a processor executing a walker process configured to traverse the searchable deterministic finite automata-based graph, the searchable deterministic finite automata-based graph including a plurality of interconnected nodes, where at least one node includes at least one valid arc; and arc configuration information stored in an arc, the arc associated with a current node and pointing from the current node to a next node, the arc configuration information representing valid arcs pointing from the next node. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A computer implemented method for traversing a deterministic finite automata-based graph comprising:
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traversing nodes in the deterministic finite automata-based graph, with a walker process, to search for an expression in an input stream; retrieving an arc associated with a current character of the input stream, the arc pointing from a current node to a next node; reading arc configuration information associated with the arc pointing from the current node to the next node and stored in the arc, the arc configuration information representing valid arcs pointing from the next node; determining if a next valid arc associated with a next character of the input stream exists in the next node based on a search indication provided by the reading; and accessing in memory the next valid arc associated with the next character if the search indication is positive.
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Specification