Normalization of floating point operations in a programmable integrated circuit device

• US 8,886,695 B1
• Filed: 07/10/2012
• Issued: 11/11/2014
• Est. Priority Date: 03/14/2008
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US13/545,405
• Time in Patent Office: 854 Days
• Field of Search: 708/497, 708552-553
• US Class Current: 708/497
• CPC Class Codes: G06F 7/4876 Multiplying
• CPC Class Codes: G06F 7/49936 Normalisation mentioned as feature only

Abstract

A programmable integrated circuit device is programmed to normalize multiplication operations by examining the input or output values to determined the likelihood of overflow or underflow and then to adjust the input or output values accordingly. The examination of the inputs can include an examination of the number of adder stages feeding into the inputs, as well as a count of leading bits ahead of the first significant bit. Adjustment of an input can include shifting the mantissa by the leading bit count and adjusting the exponent accordingly, while adjustment of the output can include shifting the mantissa by the sum of the leading bit counts of the inputs and adjusting the exponent accordingly. Or the output can be examined to find its leading bit count and the output then can be adjusted by shifting the mantissa by the leading bit count and adjusting the exponent accordingly.

Claims

1. A method of configuring a programmable integrated circuit device to perform a floating point multiplication operation on multiplicand input values to provide an output value, said method comprising:

configuring logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation; and

configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust at least one of said values to prevent overflow/underflow of said multiplication operation.

2. The method of claim 1 wherein:

said multiplicand input values have a number of overflow bits;

said configuring logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation comprises configuring said logic to compare said number of overflow bits to a number of adder stages feeding each said multiplicand input; and

said configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one said values to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to, when said number of adder stages exceeds said number of overflow bits, shift a mantissa of at least one of said multiplicand input values and adjust a respective exponent of said at least one of said multiplicand input values accordingly.

3. The method of claim 1 wherein:

said configuring logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation comprises configuring said logic to count bits to a first significant bit in each of said multiplicand input values to provide a respective bit count; and

said configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to shift a respective mantissa of at least one of said multiplicand input values by said respective bit count and adjust a respective input exponent of said at least one of said multiplicand input values accordingly.

4. The method of claim 1 wherein:

said configuring logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation comprises configuring said logic to count bits to a first significant bit in each of said multiplicand input values to provide a respective bit count; and

said configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to shift a mantissa of said output value by a sum of said respective bit counts and adjust an exponent of said output value accordingly.

5. The method of claim 1 wherein:

said configuring logic of said programmable integrated circuit device to examine said values comprises configuring said logic to count bits to a first significant bit in said output value to provide a bit count; and

said configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to shift a mantissa of said output value by said bit count and adjust an exponent of said output value accordingly.

6. The method of claim 1 wherein:

said configuring logic of said programmable integrated circuit device to examine said values comprises configuring said logic to examine said values bit-by-bit; and

said configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to make bit-by-bit adjustments.

7. The method of claim 1 wherein:

said configuring logic of said programmable integrated circuit device to examine said values comprises configuring said logic to examine said values by groups of bits; and

configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to make adjustments by groups of bits.

8. A programmable integrated circuit device configured to perform a floating point multiplication operation on multiplicand input values to provide an output value, said configured programmable logic device comprising:

logic configured to examine said values to determine likelihood of overflow/underflow of said multiplication operation; and

logic configured to, based on said likelihood, adjust at least one of said values to prevent overflow/underflow of said multiplication operation.

9. The programmable integrated circuit device of claim 8 wherein:

said multiplicand input values have a number of overflow bits;

said logic configured to examine said values to determine likelihood of overflow/underflow of said multiplication operation is configured to compare said number of overflow bits to a number of adder stages feeding each said multiplicand input; and

said logic configured to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation is configured to, when said number of adder stages exceeds said number of overflow bits, shift a mantissa of at least one of said multiplicand input values and adjust a respective exponent of said at least one of said multiplicand input values accordingly.

10. The programmable integrated circuit device of claim 8 wherein:

said logic configured to examine said values is configured to count bits to a first significant bit in each of said multiplicand input values to provide a respective bit count; and

said logic configured to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, is configured to shift a mantissa of at least one of said multiplicand input values by said respective bit count and adjust a respective exponent of said at least one of said multiplicand input values accordingly.

11. The programmable integrated circuit device of claim 8 wherein:

said logic configured to examine said values to determine likelihood of overflow/underflow of said multiplication operation is configured to count bits to a first significant bit in each of said multiplicand input values to provide a respective bit count; and

said logic configured to, based on said likelihood, adjust said one of said values to prevent overflow/underflow of said multiplication operation, is configured to shift said a mantissa of said output value by a sum of said respective bit counts and adjust an exponent of said output value accordingly.

12. The programmable integrated circuit device of claim 8 wherein:

said logic configured to examine said values is configured to count bits to a first significant bit in said output value to provide a bit count; and

said logic configured to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, is configured to shift a mantissa of said output value by said bit count and adjust an exponent of said output value accordingly.

13. The programmable integrated circuit device of claim 8 wherein:

said logic configured to examine said values is configured to examine said values bit-by-bit; and

said logic configured to adjust said at least one of said values to prevent overflow/underflow is configured to make bit-by-bit adjustments.

14. The programmable integrated circuit device of claim 8 wherein:

said logic configured to examine said values is configured to examine said values by groups of bits; and

said logic configured to adjust said at least one of said values is configured to make adjustments by groups of bits.

15. A non-transitory machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable integrated circuit device to perform a floating point multiplication operation on multiplicand input values to provide an output value, said instructions comprising:

instructions to configure logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation; and

instructions to configure logic of said programmable integrated circuit device to, based on said likelihood, adjust at least one of said values to prevent overflow/underflow of said multiplication operation.

16. The non-transitory machine-readable data storage medium of claim 15 wherein:

said multiplicand values have a number of overflow bits;

said instructions to configure logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation comprise instructions to configure said logic to compare said number of overflow bits to a number of adder stages feeding each said multiplicand input; and

said instructions to configure logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, comprise instructions to configure said logic to, when said number of adder stages exceeds said number of overflow bits, shift a mantissa of at least one of said multiplicand input values and adjust a respective exponent of said at least one of said multiplicand input values accordingly.

17. The non-transitory machine-readable data storage medium of claim 15 wherein:

said instructions to configure logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation comprise instructions to configure said logic to count bits to a first significant bit in each of said multiplicand input values to provide a respective bit count; and

said instructions to configure logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, comprise instructions to configure said logic to shift a mantissa of at least one of said multiplicand input values and adjust a respective exponent of said at least one of said multiplicand input values accordingly.

18. The non-transitory machine-readable data storage medium of claim 15 wherein:

said instructions to configure logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation comprise instructions to configure said logic to count bits to a first significant bit in each of said multiplicand input values to provide a respective bit count; and

said instructions to configure logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, comprise instructions to configure said logic to shift a mantissa of said output value by a sum of said respective bit counts and adjust an exponent of said output value accordingly.

19. The non-transitory machine-readable data storage medium of claim 15 wherein:

said instructions to configure logic of said programmable integrated circuit device to examine said values to determine likelihood of overflow/underflow of said multiplication operation comprise instructions to configure said logic to count bits to a first significant bit in said output value to provide a bit count; and

said instructions to configure logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, comprises configuring said logic to shift a mantissa of said output value by said bit count and adjust an exponent of said output value accordingly.

20. The non-transitory machine-readable data storage medium of claim 15 wherein:

said instructions to configure logic of said programmable integrated circuit device to examine said values comprises a respective one of (a) configuring said logic to examine said values bit-by-bit, or (b) configuring said logic to examine said values by groups of bits; and

said configuring logic of said programmable integrated circuit device to, based on said likelihood, adjust said at least one of said values to prevent overflow/underflow of said multiplication operation, comprises a respective one of (a) configuring said logic to make bit-by-bit adjustments, or (b) configuring said logic to make adjustments by groups of bits.