Digital signal processing circuitry with redundancy and ability to support larger multipliers

• US 8,886,696 B1
• Filed: 03/03/2009
• Issued: 11/11/2014
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Modulus Systems LLC (Jeffrey M. Gross)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Ngo, Chuong D
• Assistant Examiner(s): SANDIFER, MATTHEW D
• Application Number:
  US12/380,853
• Time in Patent Office: 2,079 Days
• Field of Search: 326 37- 47, 708/490, 708/523, 708/603, 708620-625
• US Class Current: 708/620
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 7/52 Multiplying; Dividing G06F7/483 - G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: H01L 25/00 Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

Digital signal processing (“DSP”) circuit blocks that include multipliers of a certain basic size are augmented to enable the DSP block to perform multiplications that are larger than the basic multiplier size would otherwise permit. In some embodiments, the larger multiplication can have less than full precision. In other embodiments, the larger multiplication can have full precision by making use of some capabilities of a second DSP block.

Claims

1. Digital signal processing (“

DSP”

) block circuitry comprising;

first and second multiplier circuits;

first circuitry for selectively shifting bit positions of output signals of the first multiplier circuit relative to bit positions of output signals of the second multiplier circuit; and

first circuitry for selectively additively combining output signals of the first circuitry for selectively shifting and the second multiplier circuit, wherein the second multiplier circuit comprises;

first and second sub-multiplier circuits;

second circuitry for selectively shifting bit positions of output signals of the first sub-multiplier circuit relative to bit positions of output signals of the second sub-multiplier circuit; and

second circuitry for additively combining output signals of the second circuitry for selectively shifting and the second sub-multiplier circuit; and

wherein;

said DSP block circuitry is part of a programmable integrated circuit device having general-purpose interconnect circuitry;

said DSP clock circuitry further comprising;

redundancy circuitry for selectably allowing outputs of each one of said first and second multiplier circuits to be routed to (1) another instance of said DSP block circuitry that is immediately adjacent to that DSP block circuitry, and (2) yet another instance of said DSP block circuitry that is not immediately adjacent to that DSP block circuitry, without using said general-purpose interconnect circuitry for said routing.

2. The DSP block circuitry defined in claim 1 further comprising:

routing circuitry for deriving one set of input signals to the second sub-multiplier circuit from a selectable one of (1) one set of input signals to the first sub-multiplier circuit and (2) one set of input signals to the first multiplier circuit.

3. The DSP block circuitry defined in claim 1 further comprising:

third circuitry for selectively shifting bit positions of output signals of the second circuitry for additively combining relative to bit positions of output signals of the first multiplier circuit.

4. The DSP block circuitry defined in claim 1 further comprising:

first routing circuitry for selectively routing output signals of the first multiplier circuit to a first other instance of the DSP block circuitry; and

second routing circuitry for selectively routing signals received from the first routing circuitry of a second other instance of the DSP block circuitry to the first circuitry for selectively additively combining.

5. The DSP block circuitry defined in claim 4 further comprising:

third routing circuitry for selectively routing output signals of the second multiplier circuit to the second other instance of the DSP block circuitry, and wherein the second routing circuitry can alternatively selectively route signals received from the third routing circuitry of the first other instance of the DSP block circuitry to the first circuitry for selectively additively combining.

6. The DSP block circuitry defined in claim 4 wherein the first circuitry for selectively additively combining includes fourth circuitry for selectively shifting bit positions of signals representing an additive combination of output signals of the first circuitry for selectively shifting and the second multiplier circuit relative to output signals of the second routing circuitry.

7. The DSP block circuitry defined in claim 1 wherein the first circuitry for selectively additively combining includes fifth circuitry for selectively shifting bit positions of signals to eliminate data in bit positions below a predetermined threshold of arithmetic significance.

8. The DSP block circuitry defined in claim 1 wherein the first multiplier circuit is an 18×

18 multiplier circuit, and wherein each of the first and second sub-multiplier circuits is a 9×

18 multiplier circuit.

9. The DSP block circuitry defined in claim 8 wherein the second circuitry for selectively shifting and the second circuitry for additively combining are configurable to cooperate to cause the second multiplier circuit to operate as an 18×

18 multiplier circuit.

10. The DSP block circuitry defined in claim 9 wherein the second circuitry for selectively shifting and the second circuitry for additively combining are alternatively configurable to cooperate to cause the second multiplier circuit to produce a sum of two 9×

18 multiplications.

11. The DSP block circuitry defined in claim 10 wherein the first and second multiplier circuitry and the first circuitry for selectively additively combining are configurable to cooperate to produce a product of a 27-bit multiplicand times a 27-bit multiplier, except for a partial product of 9 less-significant bits of the multiplicand and 9 less-significant bits of the multiplier.

12. The DSP block circuitry defined in claim 11 wherein the first circuitry for selectively additively combining includes circuitry for selectively truncating the product to its 27 more-significant bits.

13. The DSP block circuitry defined in claim 11 wherein the first circuitry for selectively additively combining includes circuitry for selectively receiving the partial product from another instance of the DSP block circuitry, whereby the DSP block circuitry is configurable so that the product includes the partial product.

14. The DSP block circuitry defined in claim 11 further comprising:

a third multiplier circuit for producing the partial product of 9 less-significant bits of the multiplicand and 9 less-significant bits of the multiplier, and for applying that partial product to the first circuitry for selectively additively combining, whereby the DSP block circuitry is configurable so that the product includes that partial product.

15. The DSP block circuitry defined in claim 1 further comprising:

circuitry for selectively keeping output signals of the first multiplier circuit separate from other signals in the first circuitry for selectively additively combining so that the first circuitry for selectively additively combining does not additively combine the output signals of the first and second multiplier circuits if desired.

16. A plurality of digital signal processing (“

DSP”

) block circuits, each of the DSP block circuits comprising;

first and second multiplier circuits;

first routing circuitry for outputting signals from a selectable one of (1) the first multiplier circuit in a first other one of the DSP block circuits and (2) the second multiplier circuit in a second other one of the DSP block circuits; and

first circuitry to which is input (a) output signals of the first and second multiplier circuits and (b) output signals of the first routing circuitry, for additively combining the output signals of the first and second multiplier circuits and the output signals of the first routing circuitry with relative arithmetic significance selectable from among three levels of relative arithmetic significance;

wherein;

said plurality of DSP block circuits are part of a programmable integrated circuit device having general-purpose interconnect circuitry;

each of said DSP block circuits further comprising;

redundancy circuitry for selectably allowing outputs of each one of said first and second multiplier circuits to be routed to (1) another one of said DSP block circuits that is immediately adjacent to that DSP block circuit, and (2) yet another one of said DSP block circuits that is not immediately adjacent to that DSP block circuit, without using said general-purpose interconnect circuitry for said routing.

17. The plurality of DSP block circuits defined in claim 16 wherein the first routing circuitry obtains output signals from the first multiplier circuitry in the first other one of the DSP block circuits prior to any operation on those output signals by the first circuitry for additively combining in the first other one of the DSP block circuits.

18. Digital signal processing (“

DSP”

) block circuitry comprising;

first and second multiplier circuits; and

first circuitry for selectively additively combining output signals of the first and second multiplier circuits with selectable relative arithmetic significance, wherein the second multiplier circuit comprises;

first and second sub-multiplier circuits, and

second circuitry for additively combining output signals of the first and second sub-multiplier circuits with selectable relative arithmetic significance; and

wherein;

said DSP block circuitry is part of a programmable integrated circuit device having general-purpose interconnect circuitry;

said DSP block circuitry further comprising;

redundancy circuitry for selectably allowing outputs of each one of said first and second multiplier circuits to be routed to (1) another instance of said DSP block circuitry that is immediately adjacent to that DSP block circuitry, and (2) yet another instance of said DSP block circuitry that is not immediately adjacent to that DSP block circuitry, without using said general-purpose interconnect circuitry for said routing.

19. The DSP block circuitry defined in claim 18 further comprising:

routing circuitry for deriving one set of input signals to the second sub-multiplier circuit from a selectable one of (1) one set of input signals to the first sub-multiplier circuit and (2) one set of input signals to the first multiplier circuit.

20. The DSP block circuitry defined in claim 18 wherein the first circuitry for selectively combining is alternatively able to output separate first and second product signals for the first and second multiplier circuits, respectively.

21. The DSP block circuitry defined in claim 18 wherein the first circuitry for selectively combining is able to selectively truncate signals having arithmetic significance below a predetermined threshold level.