Apparatus and method of page program operation for memory devices with mirror back-up of data

• US 8,886,871 B2
• Filed: 09/30/2011
• Issued: 11/11/2014
• Est. Priority Date: 02/22/2007
• Status: Expired due to Fees

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Pyeon, Hong Beom, Kim, Jin-Ki, Oh, HakJune
• Primary Examiner(s): DUDEK JR, EDWARD J
• Application Number:
  US13/250,301
• Publication Number:
  US 20120023286A1
• Time in Patent Office: 1,138 Days
• Field of Search: 711/103, 711/118, 711/154, 711/E12.008, 710/52
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4247 on a daisy chain bus

Abstract

An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

Claims

1. A system comprising:

a controller; and

a serial interconnection of first to N-th devices connected in-series configured to communicate with the controller, N being an integer greater than one, each of the N devices being associated with a device identification and selectable based on the device identification, each of the N devices comprising;

a store element for storing data,

a first input for receiving an input control signal from a previous device,

a first output for outputting an output control signal derived from the input control signal to a succeeding device,

a second input for receiving an input command signal from the previous device,

a second output for outputting an output command signal to the succeeding device, the received command signal being propagated to the succeeding device based on device selection determination in response to the input and output control signals, and

a third input for receiving a clock signal to perform operations of the receiving and outputting by the device,

the controller being configured

to send a first input control signal to the first input of the first device of the serial interconnection as the input control signal of the first device,

to send a first command signal to the second input of the first device of the serial interconnection as the input command signal of the first device;

the first command signal including;

a first device address identification for device selection;

an operation instruction for storing data; and

first data to be written, the first device address identification,

wherein, the first device address identification, the operation instruction and the first data form a modular command structure, and

to send a second input control signal to the first input of the first device of the serial interconnection as the input control signal of the first device,

to send a second command signal to the second input of the first device of the serial interconnection as the input command signal of the first device;

the second command signal including;

a second device address identification for device selection;

an operation instruction for storing data; and

second data to be written,

wherein,

the second device address identification, the operation instruction and the second data form a modular command structure,

the second device address identification is different from the first device address identification, and

the second data corresponds to the first data,

an i-th device (1≦

i≦

N) of the serial interconnection being configured

to receive the first command signal sent by the controller or propagated from the previous device and capture the first command signal received at the second input in response to the input control signal received at the first input of the i-th device;

to output the output control signal to the first output, the output control signal being received as the input control signal of the succeeding device;

to determine whether the i-th device is selected based on the first device address identification included in the captured first command signal and the associated device identification;

to process the operation instruction included in the captured first command signal, the first data included in the captured first command signal being stored in the store element comprised in the i-th device, in a case of determination where the i-th device is selected; and

to forward the captured first command signal including the first device address identification, the operation instruction and the first data formed in a modular command structure through the second output of the i-th device to the succeeding device, in a case of determination where the i-th device is not selected,

a j-th device (1≦

j≦

N, j≠

i) of the serial interconnection being configured

to receive the second command signal sent by the controller or propagated from the previous device and capture the second command signal received at the second input in response to the input control signal received at the first input of the j-th device;

to determine whether the j-th device is selected based on the second device address identification included in the captured second command signal and the associated device identification;

to process the operation instruction included in the captured second command signal, the second data included in the captured second command signal being stored in the store element comprised in the j-th device, in a case of determination where the j-th device is selected; and

to forward the captured second command signal including the second device address identification, the operation instruction and the second data formed in a modular command structure through the second output of the j-th device to the succeeding device, in a case of determination where the j-th device is not selected.

2. The system of claim 1, wherein the second data is the same data as the first data.

3. The system of claim 2, wherein the controller is configured to send the second command signal after the first command signal.

4. The system of claim 3, wherein each of the N devices further comprises memory cells and the i-th device is further configured to write the first data stored in the store element in the memory cells of the selected i-th device.

5. The system of claim 4, wherein the controller is further configured to recover the second data stored in the store element of the j-th device, in a case of failure of the data writing in the selected i-th device, the recovered data being propagated through the second output of the i-th device to the N-th device of the serial interconnection, the recovered data being further forwarded from the second output of the N-th device to the controller.

6. The system of claim 5, wherein the controller is further configured to send a third command signal to the first device of the serial interconnection, the third command signal including:

a third device address identification for selection of the i-th device;

the operation instruction for storing data; and

third data to be written,

wherein,

the third device address identification, the operation instruction and the third data forms a modular command structure, and

the third data is the same as the recovered data.

7. The system of claim 6, wherein the i-th device is further configured to:

receive the third command signal sent by the controller or propagated from a previous device; and

process the operation instruction included in the received third command signal, the third data included in the received third command signal being stored in the store element comprised in the i-th device.

8. The system of claim 7, wherein the i-th device is further configured to program the third data stored in the store element to write in the memory cells of the i-th device.

9. The system of claim 8, wherein each of the N devices comprises a non-volatile memory device.

10. The system of claim 9, wherein the non-volatile memory device comprises a flash device.

11. The system of claim 10, wherein the flash device comprises a page buffer as the store element and the memory cells.