Periodic error detection method and periodic error detection circuit

• US 8,887,004 B2
• Filed: 03/13/2012
• Issued: 11/11/2014
• Est. Priority Date: 10/28/2011
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Terayama, Tomoyuki
• Primary Examiner(s): PATEL, KAMINI B
• Application Number:
  US13/419,388
• Publication Number:
  US 20130111276A1
• Time in Patent Office: 973 Days
• Field of Search: 714/47.1
• US Class Current: 714/47.1
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

According to one embodiment, a method for detecting a periodic error, the method detecting a periodic processing error of a module controlled by a processor, the processor controlling a periodic processing by booting a peripheral module, the peripheral module outputting periodic triggers with a predetermined interval includes storing a first count value acquired from a counter, a second count value when the processing is started, and a third count value when the processing is completed, calculating a processing time on a basis of the three count values, and comparing the processing time with the predetermined interval to determine whether the periodic processing error occurs.

Claims

1. A method for detecting a periodic error, the method detecting a periodic processing error of a module, execution of processing of the module being controlled by a processor, the processor controlling a periodic processing by booting a peripheral module, the peripheral module outputting periodic triggers with a predetermined interval, comprising:

storing a first count value in a register included in a capture timer, the first count value being acquired from a counter included in the capture timer by outputting the periodic triggers as a first capture trigger into the capture timer, the counter performing an up-count operation with free-run;

storing a second count value in the register, the second count value being acquired from the counter by outputting a second capture trigger into the capture timer when the processing of the module is started;

storing a third count value in the register, the third count value being acquired from the counter by outputting a third capture trigger into the capture timer when the processing of the module is completed;

reading out the first count value, the second count value and the third count value from the register when the processor receives a complete notice from the module;

calculating a processing time by adding a first value to a second value, wherein the first value is equal to the second count value minus the first count value, and the second value is equal to the third count value minus the second count value;

comparing the processing time with the predetermined interval; and

determining that the periodic processing error has occurred when the processing time is greater than or equal to the predetermined interval.

2. The method of claim 1, wherein

the processor includes and executes a periodic error detection program to determine an occurrence of the periodic processing error when the processing time is greater than or equal to the predetermined interval.

3. The method of claim 2, wherein the periodic error detection program includes a first function that, when executed,

calculates the processing time by adding the first value and the second value,

compares the processing time with the predetermined interval, and

based on the comparison, determines that the processing time is greater than or equal to the predetermined interval, wherein the determination indicates an occurrence of a periodic processing error.

4. The method of claim 3, wherein the periodic error detection program includes a second function that, when executed, detects an overflow of the counter and

determines the occurrence of the periodic processing error when each of the following inequalities is not satisfied:

0≦

(cnt2+ovfl−

cnt1)+(cnt3−

cnt2)≦

T; and

 

 

(1)

0≦

(cnt2−

cnt1)+(cnt3+ovfl−

cnt2)≦

T, 

 

(2)

wherein cnt1, cnt2, cnt3, ovfl, and T are, respectively, the first count value, the second count value, the third count value, an overflow value, and the predetermined interval.

5. The method of claim 1, wherein

a determination circuit connected between the processor and the capture timer determines an occurrence of the periodic processing error when the processing time is greater than or equal to the predetermined interval.

6. The method of claim 1, wherein

the peripheral module is a motor control circuit controlling motor driving and the module is a vector engine executing calculation on vector control of a motor.

7. The method of claim 6, wherein

the motor control circuit performs a first interruption to the processor when the periodic triggers are output, the processor enables the vector engine corresponding to the first interruption, and the vector engine performs a second interruption to the processor when the processing is completed.

8. A periodic error detection circuit, comprising:

a peripheral module outputting periodic triggers with a predetermined interval;

a processor controlling periodic processing by booting the peripheral module;

a module, execution of processing of the module being controlled by the processor;

a capture timer including a counter and a register, the counter performing an up-count operation with free-run, the register storing a first count value, the first count value being acquired from the counter by outputting the periodic triggers as a first capture trigger, storing a second count value, the second count value being acquired from the counter by outputting a second capture trigger when the processing of the module is started, and storing a third count value, the third count value being acquired from the counter by outputting a third capture trigger when the processing of the module is completed; and

a determination circuit connected between the processor and the capture timer, wherein the determination circuit is configured to;

calculate a processing time by adding a first value to a second value, wherein the first value is equal to the second count value minus the first count value, and the second value is equal to the third count value minus the second count value;

compare the processing time with the predetermined interval;

based on the comparison, determine that the periodic processing error has occurred when the processing time is greater than or equal to the predetermined interval.

9. The periodic error detection circuit of claim 8, wherein

the determination circuit including a first subtracter which subtracts the first count value from the second count value,

a second subtracter which subtracts the second count value from the third count value,

an adder which adds an input of the first subtracter and an input of the second subtracter to obtain the processing time,

and a comparator that compares the processing time with the predetermined interval to determine an occurrence of the periodic processing error when the processing time is equal to or greater than or equal to the predetermined interval.

10. The periodic error detection circuit of claim 8, wherein

the module is a vector engine executing calculation on vector control of a motor and the peripheral module is a motor control circuit controlling motor driving.

11. The periodic error detection circuit of claim 10, wherein

the motor control circuit performs a first interruption to the processor when the periodic triggers are output, the processor enables the vector engine corresponding to the first interruption, and the vector engine performs a second interruption to the processor when the processing is completed.

12. A periodic error detection circuit, comprising:

a peripheral module outputting periodic triggers with an predetermined interval;

a processor controlling periodic processing by booting a peripheral module and executing a periodic error detection program to determine an occurrence of a periodic processing error;

a module, execution of processing of the module being controlled by the processor;

a capture timer including a counter and a register, the counter performing an up-count operation with free-run, the register storing a first count value, the first count value being acquired from the counter by outputting the periodic triggers as a first capture trigger, storing a second count value, the second count value being acquired from the counter by outputting a second capture trigger when the processing of the module is started, and storing a third count value, the third count value being acquired from the counter by outputting a third capture trigger when the processing of the module is completed, wherein

the processor is configured to;

read the first count value, the second count value, and the third count value from the register upon receiving a completion notice from the module;

calculate a processing time by adding a first value to a second value, wherein the first value is equal to the second count value minus the first count value, and the second value is equal to the third count value minus the second count value;

compare the processing time with the predetermined interval; and

based on the comparison, determine that the periodic processing error has occurred when the processing time is greater than or equal to the predetermined interval.

13. The periodic error detection circuit of claim 12, wherein

the periodic error detection program includes a first function that, when executed, calculates the processing time by adding the first value to the second value and

compares the processing time to the predetermined interval to determine the occurrence of the periodic processing error when the processing time is greater than or equal to the predetermined interval.

14. The periodic error detection circuit of claim 13, wherein

the periodic error detection program further includes a second function that, when executed, detects an overflow of the counter and

determines the occurrence of the periodic processing error when each of the following inequalities is not satisfied:

0≦

(cnt2+ovfl−

cnt1)+(cnt3−

cnt2)≦

T; and

 

 

(1)

0≦

(cnt2−

cnt1)+(cnt3+ovfl−

cnt2)≦

T, 

 

(2)

wherein cnt1, cnt2, cnt3, ovfl, and T are, respectively, the first count value, the second count value, the third count value, an overflow value, and the predetermined interval.

15. The periodic error detection circuit of claim 12, wherein

the module is a vector engine executing calculation on vector control of a motor and the peripheral module is a motor control circuit controlling motor driving.

16. The periodic error detection circuit of claim 15, wherein

the motor control circuit performs a first interruption to the processor when the periodic triggers are output, the processor enables the vector engine corresponding to the first interruption, and the vector engine performs a second interruption to the processor when the processing is completed.