Apparatus and method for designing semiconductor device, and semiconductor device

• US 8,887,015 B2
• Filed: 07/09/2012
• Issued: 11/11/2014
• Est. Priority Date: 07/15/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Iwata, Hiroyuki, Matsushima, Jun
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US13/544,491
• Publication Number:
  US 20130019134A1
• Time in Patent Office: 855 Days
• Field of Search: 714/726, 714/728, 714/724, 714/725, 714/729, 714/738, 714/739
• US Class Current: 714/726
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]

Abstract

An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced.

Claims

1. A method of designing a semiconductor device including a scan flip-flop circuit that can switch between scanning operation and capturing operation, the method causing an arithmetic processor to execute the steps of:

analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state; and

structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing step,

wherein the method causes the arithmetic processor to execute a fixed value masking function addition step of adding a maskable mask control logic to a logical value higher in the probability provided to the scan flip-flop circuit included in each scan chain after the capturing operation, on the basis of information on the probability that each scan flip-flop circuit configuring the scan chain becomes the given logical state after the scan chain structuring step has been executed by the arithmetic processor.

2. The method of designing a semiconductor device according to claim 1, wherein the method causes the arithmetic processor to execute a substitution step of substituting the scan flip-flop circuit with a scan flip-flop circuit that can reduce an electric power by enabling the clock mask when a logical value higher in the probability provided to the scan flip-flop circuit included in each scan chain after the capturing operation is continuously input, on the basis of information on the probability that each scan flip-flop circuit configuring the scan chain becomes the given logical state after the compression scan addition step has been executed by the arithmetic processor.

3. The method of designing a semiconductor device according to claim 2, wherein the method causes the arithmetic processor to execute a step of inserting a test point circuit that can control the probability that the output value of the scan flip-flop circuit after the capturing operation becomes the given logical state.

4. The method of designing a semiconductor device according to claim 1, wherein the method causes the arithmetic processor to execute a substitution step of substituting the scan flip-flop circuit with a scan flip-flop circuit that can reduce an electric power by enabling the clock mask when a logical value higher in the probability provided to the scan flip-flop circuit included in each scan chain after the capturing operation is continuously input, on the basis of information on the probability that each scan flip-flop circuit configuring the scan chain becomes the given logical state after the scan chain structuring step has been executed by the arithmetic processor.

5. A designing apparatus that can design a semiconductor device including a scan flip-flop circuit that can switch between scanning operation and capturing operation, the apparatus comprising:

an arithmetic processor that can execute given processing according to a predetermined program, wherein the arithmetic processor executes;

analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state; and

scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analysis processing.

6. The designing apparatus according to claim 5, wherein the arithmetic processor executes fixed value masking function addition processing of adding a maskable mask control logic to a logical value higher in the probability provided to the scan flip-flop circuit included in each scan chain after the capturing operation, on the basis of information on the probability that each scan flip-flop circuit configuring the scan chain becomes the given logical state after the scan chain structure processing has been executed.

7. The designing apparatus according to claim 6, wherein the arithmetic processor executes substitution processing of substituting the scan flip-flop circuit with a scan flip-flop circuit that can reduce an electric power by enabling the clock mask when a logical value higher in the probability provided to the scan flip-flop circuit included in each scan chain after the capturing operation is continuously input, on the basis of information on the probability that each scan flip-flop circuit configuring the scan chain becomes the given logical state after the compression scan addition processing has been executed.

8. The designing apparatus according to claim 5, wherein the arithmetic processor executes substitution processing of substituting the scan flip-flop circuit with a scan flip-flop circuit that can reduce an electric power by enabling the clock mask when a logical value higher in the probability provided to the scan flip-flop circuit included in each scan chain after the capturing operation is continuously input, on the basis of information on the probability that each scan flip-flop circuit configuring the scan chain becomes the given logical state after the scan chain structuring processing has been executed.

9. A semiconductor device comprising:

a scan flip-flop circuit that can switch between scanning operation and capturing operation,

wherein a scan chain is structured for a plurality of scan flip-flop circuits having the same degree of probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state,

wherein a maskable mask control logic is included in a logical value higher in the probability after the capturing operation.

10. The semiconductor device according to claim 9, further comprising a scan flip-flop circuit that can reduce an electric power by enabling a clock mask when a logical value higher in the probability after the capturing operation is continuously input.

11. The semiconductor device according to claim 10, further comprising a test point circuit that can control the probability that the output value of the scan flip-flop circuit after the capturing operation becomes the given logical state.