Masking circuit removing unknown bit from cell in scan chain

• US 8,887,018 B2
• Filed: 10/14/2010
• Issued: 11/11/2014
• Est. Priority Date: 06/11/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Narayanan, Prakash, Jain, Arvind, Subramanian, Sundarrajan, Parekhji, Rubin A.
• Primary Examiner(s): Bonzo, Bryce
• Assistant Examiner(s): Mehrmanesh, Elmira
• Application Number:
  US12/904,303
• Publication Number:
  US 20110307750A1
• Time in Patent Office: 1,489 Days
• Field of Search: 714725-731, 714/738
• US Class Current: 714/729
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Claims

1. Electronic scan circuitry comprising:

a decompressor;

a plurality of scan chains fed by the decompressor;

a scan circuit coupled to the plurality of scan chains to scan them in and out;

a masking circuit fed by the scan chains;

a scannable masking qualification circuit coupled to the masking circuit, the masking qualification circuit scannable by scan-in of scan chain cell qualifying bits by the decompressor along with scan-in of the scan chains, and the scannable masking qualification circuit operable to hold such scanned-in scan chain cell qualifying bits upon scan-out of the scan chains through the masking circuit; and

the masking circuit is, in response to the scan chain cell qualifying bits, for removing an unknown bit from a single cell in a single scan chain in the plurality of scan chains.

2. The electronic scan circuitry claimed in claim 1 including a control signal generator operable to supply a varying control signal to the masking qualification circuit upon scan-out to qualify and disqualify one or more cells in the scan chains on various scan cycles.

3. The electronic scan circuitry claimed in claim 1 including a compactor fed by the masking circuit and by part of the scannable masking qualification circuit, the compactor operable for compaction upon scan-out of such scanned-in scan chain cell qualifying bits in the scannable masking qualification circuit while another part of the scannable masking qualification circuit holds such scanned-in scan chain cell qualifying bits.

4. The electronic scan circuitry claimed in claim 1 in which the scannable masking qualification circuit has a shift register including a set of shift register cells, each cell in the set operable to select a plurality of scan chains corresponding to such cell for qualification or disqualification in tandem.