Method for manufacturing semiconductor device

• US 8,889,503 B2
• Filed: 12/12/2013
• Issued: 11/18/2014
• Est. Priority Date: 06/13/2011
• Status: Expired due to Fees

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Yoneda, Kenji
• Primary Examiner(s): Patel, Reema
• Assistant Examiner(s): GHEYAS, SYED I
• Application Number:
  US14/104,289
• Publication Number:
  US 20140106521A1
• Time in Patent Office: 341 Days
• Field of Search: 438/514, 257/E21.342
• US Class Current: 438/198
• CPC Class Codes: H01J 2237/20207 Tilt
• CPC Class Codes: H01J 2237/24528 Direction of beam or parts thereof in view of the optical axis, e.g. beam angle, angular distribution, beam divergence, beam convergence or beam landing angle on sample or workpiece
• CPC Class Codes: H01J 2237/31701 Ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/68764 characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating caroussel
• CPC Class Codes: H01L 21/68771 characterised by supporting more than one semiconductor substrate
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has Off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface.

Claims

1. A method for manufacturing a semiconductor device which includes, on a semiconductor substrate having a notch, a plurality of transistors in parallel with and perpendicular to a notch direction extending between a center of the semiconductor substrate and the notch, the method comprising:

preparing the semiconductor substrate which has a front surface having an Off angle of at least 2 degrees and at most 2.8 degrees from (100) plane in a direction in which a Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and

doping impurities into the front surface of the semiconductor substrate in a direction perpendicular to the front surface.

2. The method for manufacturing the semiconductor device according to claim 1,

wherein the Twist angle is 22.5 degrees.

3. The method for manufacturing the semiconductor device according to claim 1,

wherein the notch is formed at a periphery of the semiconductor substrate in <

0-11>

direction, and

the plurality of transistors are formed on the semiconductor substrate in the <

0-11>

direction and <

011>

direction, or in <

001>

direction and <

010>

direction.

4. The method for manufacturing the semiconductor device according to claim 1,

wherein the notch is formed at a periphery of the semiconductor substrate in <

0-11>

direction, and

the plurality of transistors are formed on the semiconductor substrate in the <

0-11>

direction, <

011>

direction, <

001>

direction, and <

010>

direction.

5. The method for manufacturing the semiconductor device according to claim 1,

wherein an error angle of the Off angle is within ±

0.1 degree.

6. The method for manufacturing the semiconductor device according to claim 1,

wherein the vertical direction is a direction of 0±

0.15 degree relative to the front surface of the semiconductor substrate.

7. The method for manufacturing the semiconductor device according to claim 1,

wherein doping the impurities is to form channel regions of the plurality of transistors.

8. The method for manufacturing the semiconductor device according to claim 1,

wherein doping the impurities is to form source-drain regions of the plurality of transistors.

9. The method for manufacturing the semiconductor device according to claim 1,

wherein doping the impurities is to form extension regions of the plurality of transistors.

10. The method for manufacturing the semiconductor device according to claim 2,

wherein the notch is formed at a periphery of the semiconductor substrate in <

0-11>

direction, and

the plurality of transistors are formed on the semiconductor substrate in the <

0-11>

direction and <

011>

direction, or in <

001>

direction and <

010>

direction.

11. The method for manufacturing the semiconductor device according to claim 2,

wherein the notch is formed at a periphery of the semiconductor substrate in <

0-11>

direction, and

the plurality of transistors are formed on the semiconductor substrate in the <

0-11>

direction, <

011>

direction, <

001>

direction, and <

010>

direction.

12. The method for manufacturing the semiconductor device according to claim 2,

wherein an error angle of the Off angle is within ±

0.1 degree.

13. The method for manufacturing the semiconductor device according to claim 2,

wherein the vertical direction is a direction of 0±

0.15 degree relative to the front surface of the semiconductor substrate.

14. The method for manufacturing the semiconductor device according to claim 2,

wherein doping the impurities is to form channel regions of the plurality of transistors.

15. The method for manufacturing the semiconductor device according to claim 2,

wherein doping the impurities is to form source-drain regions of the plurality of transistors.

16. The method for manufacturing the semiconductor device according to claim 2,

wherein doping the impurities is to form extension regions of the plurality of transistors.