Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

• US 8,889,504 B2
• Filed: 02/02/2012
• Issued: 11/18/2014
• Est. Priority Date: 03/13/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Dyer, Thomas W, Yang, Haining S
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): Cruz, Leslie Pilar
• Application Number:
  US13/364,753
• Publication Number:
  US 20120135591A1
• Time in Patent Office: 1,020 Days
• Field of Search: 438/151, 438/154, 438/197, 438/199, 438/585, 438/587, 438/931, 438/938, 257/288, 257/413, 257/E29.156, 257/E29.134, 257/E29.161, 257/E21.177, 257/E21.622, 257/E21.636, 257/E21.637, 257/E29.126, 257/E29.128, 257/1.176, 257/E21.194
• US Class Current: 438/199
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.

Claims

1. A method of forming a semiconductor structure comprising:

forming sidewalls and spacers adjacent to a gate stack structure;

forming a recess in the gate stack structure;

epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure; and

relaxing the epitaxially-grown straining material such that a lattice constant of the straining material is an intrinsic lattice constant of Si;

C that is smaller than a lattice constant of the polysilicon layer,

wherein the straining material is Si;

C and the gate stack structure is a PFET gate stack structure,

wherein the straining material is grown above and covering a top surface of the sidewalls and the spacers, and

wherein the method further comprises;

forming a gate oxide layer on a wafer of the semiconductor structure;

forming the polysilicon layer on the gate oxide layer; and

forming a SiGe layer on the polysilicon layer.

2. The method of claim 1, further comprising patterning the gate oxide layer, the polysilicon layer, and the SiGe layer to form the gate stack structure.

3. The method of claim 2, further comprising removing the SiGe layer from the gate stack structure to form the recess in the gate stack structure.

4. The method of claim 1, further comprising:

forming a resist on the SiGe layer; and

exposing one or more selective portions of the resist to form one or more openings in the resist.

5. The method of claim 4, further comprising patterning the gate oxide layer, the polysilicon layer, and the SiGe layer to form the gate stack structure based on the one or more openings.

6. The method of claim 1, wherein:

the sidewalls are oxide; and

the spacers are silicon nitride.

7. The method of claim 1, wherein the straining material is substantially planar above a surface of the semiconductor structure.

8. The method of claim 7, wherein the straining material extends laterally over and above the sidewalls and the spacers.

9. A method of forming a semiconductor structure comprising:

forming sidewalls and spacers adjacent to a gate stack structure;

forming a recess in the gate stack structure;

epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure; and

relaxing the epitaxially-grown straining material such that a lattice constant of the straining material is an intrinsic lattice constant of Si;

C that is smaller than a lattice constant of the polysilicon layer,

wherein the straining material is Si;

C and the gate stack structure is a PFET gate stack structure,

wherein the straining material is grown above and covering a top surface of the sidewalls and the spacers, and

wherein the method further comprises;

forming second sidewalls and second spacers adjacent to a second gate stack structure;

forming a recess in the second gate stack structure;

epitaxially growing a second straining material on a polysilicon layer of the second gate stack structure, and in the recess in the second gate stack structure; and

relaxing the second straining material such that an intrinsic lattice constant of the second straining material is larger than a lattice constant of the polysilicon layer of the second gate stack structure,

wherein the second straining material is SiGe and the second gate stack structure is an NFET gate stack structure.