Methods of manufacturing power semiconductor devices with trenched shielded split gate transistor

• US 8,889,511 B2
• Filed: 08/26/2011
• Issued: 11/18/2014
• Est. Priority Date: 05/20/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Kraft, Nathan L.
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US13/219,229
• Publication Number:
  US 20110312138A1
• Time in Patent Office: 1,180 Days
• Field of Search: 438/270
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

In one general aspect, a method can include forming a shield dielectric layer in a trench in a semiconductor substrate, forming a shield electrode on at least a portion of the shield dielectric layer, and etching the shield dielectric layer so that a portion of the shield dielectric layer is recessed in the trench. The method can include forming a gate dielectric layer on the recessed portion of the shield dielectric layer in the trench, forming a first conductive gate electrode on a first side of the shield electrode and insulated from a first sidewall of the trench by the gate dielectric layer, and forming a second conductive gate electrode on a second side of the shield electrode and insulated from a second sidewall of the trench by the gate dielectric layer.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming a shield dielectric layer in a trench in a semiconductor substrate;

forming a shield electrode on at least a portion of the shield dielectric layer;

etching the shield dielectric layer so that a portion of the shield dielectric layer is recessed in the trench;

forming a gate dielectric layer on the recessed portion of the shield dielectric layer in the trench;

forming a first conductive gate electrode on a first side of the shield electrode and insulated from a first sidewall of the trench by the gate dielectric layer;

forming a second conductive gate electrode on a second side of the shield electrode and insulated from a second sidewall of the trench by the gate dielectric layer such that the shield electrode has a first portion disposed lower in the trench than a bottom portion of the second conductive gate electrode and such that the shield electrode has a second portion disposed higher in the trench than a top portion of the second conductive gate electrode;

forming a source contact in contact with the second portion of the shield electrode;

forming a well region in contact with the first sidewall of the trench;

forming a source region in contact with the first sidewall of the trench and inside the well region; and

forming an electrical contact between the shield electrode and the well region inside a mesa via a body trench adjacent to the trench.

2. The method of claim 1, wherein the forming the well region is performed with a p-well implant.

3. The method of claim 1, wherein the forming the source region is performed with an n+ source implant.

4. The method of claim 1, further comprising depositing a layer of borophosphosilicate glass (BPSG).

5. The method of claim 1, further comprising performing a contact etch and a p+ heavy body implant.

6. The method of claim 1, further comprising metallizing at least one surface to form the source contact.

7. The method of claim 1, wherein the gate dielectric layer forms a trough on each side of the shield electrode inside the trench.

17. The method of claim 1, wherein the semiconductor substrate includes silicon carbide.

8. A method, comprising:

forming a trench having a first trench sidewall and a second trench sidewall;

forming a shield dielectric layer on the first trench sidewall, a bottom surface of the trench, and the second trench sidewall;

forming a conductive shield electrode having a bottom portion disposed on the shield dielectric layer and having a top portion;

forming a gate dielectric layer on at least a portion of the shield dielectric layer;

forming a first conductive gate electrode on a first side of the conductive shield electrode and insulated from the first trench sidewall by the gate dielectric layer;

forming a second conductive gate electrode on a second side of the conductive shield electrode and insulated from the second trench sidewall by the gate dielectric layer;

forming a source metal in contact with the top portion of the conductive shield electrode, the conductive shield electrode extending vertically from the bottom portion disposed on the shield dielectric layer to the top portion in contact with the source metal, the source metal being insulated from first conductive gate electrode and insulated from the second conductive gate electrode;

forming a well region in contact with the first trench sidewall;

forming a source region in contact with the first trench sidewall and inside the well region; and

forming an electrical contact between the conductive shield electrode and the well region inside a mesa via a body trench adjacent to the trench.

9. The method of claim 8, wherein the bottom portion of the conductive shield electrode extends deeper into the trench than bottom portion of the first conductive gate electrode and the top portion of the conductive shield electrode is disposed higher in the trench than a top portion of the first conductive gate electrode.

10. The method of claim 8, wherein the conductive shield electrode is disposed between the first conductive gate electrode and the second conductive gate electrode.

11. The method of claim 8, further comprising:

forming a drift region of a first conductivity type, the forming the well region including forming the well region above the drift region, the well region having a second conductivity type opposite the first conductivity type, at least a portion of the trench being disposed in the well region and being disposed in the drift region.

12. The method of claim 8, further comprising:

forming a body trench extending deeper into the well region than the source region.

18. The method of claim 8, wherein the forming the trench includes forming the trench in silicon carbide.

13. A method, comprising:

forming a trench having a first trench sidewall and a second trench sidewall;

forming a first conductive gate electrode disposed along and insulated from the first trench sidewall;

forming a second conductive gate electrode disposed along and insulated from the second trench sidewall;

forming a conductive shield electrode disposed between the first conductive electrode and the second conductive gate electrode, the conductive shield electrode having a first portion extending deeper into the trench than the first conductive gate electrode, the conductive shield electrode having a second portion disposed higher in the trench than the first conductive gate electrode and disposed vertically above the first portion of the conductive shield electrode, the second portion being in contact with a source metal;

forming a well region in contact with the first trench sidewall;

forming a source region in contact with the first trench sidewall and inside the well region; and

forming an electrical contact between the conductive shield electrode and the well region inside a mesa via a body trench adjacent to the trench.

14. The method of claim 13, wherein the first portion of the conductive shield electrode extends deeper into the trench than a bottom portion of the first conductive gate electrode.

15. The method of claim 13, wherein the second portion of the conductive shield electrode is disposed higher in the trench than a top portion of the first conductive gate electrode.

16. The method of claim 13, further comprising:

forming a drift region of a first conductivity type; and

forming the well region above the drift region, the well region having a second conductivity type opposite the first conductivity type, at least a portion of the trench being disposed in the well region and being disposed in the drift region.

19. The method of claim 13, wherein the forming the trench includes forming the trench in silicon carbide.