Method and device including transistor component having a field electrode

• US 8,889,512 B2
• Filed: 10/26/2011
• Issued: 11/18/2014
• Est. Priority Date: 10/26/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Krumrey, Joachim, Noebauer, Gerhard, Probst, Marc, Poelzl, Martin
• Primary Examiner(s): Pham, Long
• Application Number:
  US13/281,829
• Publication Number:
  US 20120040505A1
• Time in Patent Office: 1,119 Days
• Field of Search: 438/270, 438/595
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench.

Claims

1. A method of forming a transistor component, including:

providing a semiconductor arrangement including;

a semiconductor body having a first side, at least one first trench extending from the first side, and having sidewalls and lower and upper trench sections, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric, at least one second trench in the semiconductor body, the at least one second trench having sidewalls and lower and upper sidewall sections, and a second field electrode arranged in lower and upper trench sections of the at least one second trench and being insulated from the semiconductor body by the field electrode dielectric;

forming a dielectric layer on the first field electrode in the at least one first trench, forming the dielectric layer including a deposition process that deposits a dielectric material on the first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench;

forming a gate dielectric, the gate dielectric at least lining the sidewalls in the upper trench section of the at least one first trench;

forming a gate electrode in the upper trench section, gate electrode being insulated from the first field electrode by the dielectric layer.

2. The method of claim 1, wherein the dielectric layer is also deposited on the at least one second field electrode.

3. The method of claim 1, wherein forming the MOS gated diode structure includes:

forming a third field electrode in the lower and upper sections of the at least one third trench;

forming a third field electrode dielectric layer insulating the third field electrode from the semiconductor body in the lower trench section of the at least one third trench;

forming a diode gate electrode between the field electrode and the semiconductor body in the upper section of the at least one third trench, the diode gate electrode in the at least one third trench being insulated from the semiconductor body and the third field electrode by a diode gate dielectric.

4. A method of making a device comprising:

providing a semiconductor arrangement including a semiconductor body having at least one first trench extending from a first side, the at least one first trench having sidewalls and lower and upper trench sections, a first field electrode arranged in the lower trench section and being insulated from the semiconductor body by a field electrode dielectric;

forming a dielectric layer on the first field electrode including depositing a dielectric material on the first side of the semiconductor body and on the first field electrode at a higher deposition rate than on sidewalls of the at least one first trench;

forming agate dielectric, at least lining the sidewalls in the upper trench section; and

forming a gate electrode in the upper trench section, insulated from the first field electrode by the dielectric layer,

wherein forming the dielectric layer further includes;

producing a protection layer covering the dielectric layer in the at least one first trench and on the first side, the protection layer completely filling the at least one first trench;

completely removing the protection layer above the first side and at least partly removing the dielectric layer on the first side, and at least partly leaving the protection layer in the at least one first trench; and

removing the protection layer from the at least one first trench.

5. The method of claim 4, wherein completely removing the protection layer above the first side and at least partly removing the dielectric layer on the first side includes an etch process that etches the material of the protective layer and the material of the dielectric layer.

6. The method of claim 5, wherein the dielectric layer is an oxide layer, or a nitride layer.

7. The method of claim 5, wherein the protective layer is a resist layer, a carbon layer, or a carbon-containing layer.

8. The method of claim 4, wherein removing the protection layer from the at least one first trench includes an etch process that selectively etches the material of the protect layer.

9. The method of claim 4, further including:

depositing the dielectric layer on the sidewalls in the upper trench section when depositing the dielectric layer on the field plate and on the first side of the semiconductor body;

completely removing the dielectric layer from the first side of the semiconductor body and from the sidewalls of the at least one first trench after removing the protection layer before forming the gate dielectric.

10. The method of claim 4, further including:

forming source and body zones adjacent to the gate dielectric in the semiconductor body after forming the gate electrode.

11. The method of claim 4, wherein the semiconductor arrangement further includes:

at least one third trench having lower and upper trench sections, and

a MOS gated diode structure arranged in the trench.

12. A method of making a device comprising:

providing a semiconductor arrangement including a semiconductor body having at least one first trench extending from a first side, the at least one first trench having sidewalls and lower and upper trench sections, a first field electrode arranged in the lower trench section and being insulated from the semiconductor body by a field electrode dielectric;

forming a dielectric layer on the first field electrode including depositing a dielectric material on the first side of the semiconductor body and on the first field electrode at a higher deposition rate than on sidewalls of the at least one first trench;

forming a gate dielectric, at least lining the sidewalls in the upper trench section; and

forming a gate electrode in the upper trench section, insulated from the first field electrode by the dielectric layer;

wherein the semiconductor arrangement further includes;

at least one third trench having lower and upper trench sections, and

a MOS gated diode structure arranged in the trench.

13. The method of claim 12, wherein forming the dielectric layer further includes:

producing a protection layer covering the dielectric layer in the at least one first trench and on the first side, the protection layer completely filling the at least one first trench;

completely removing the protection layer above the first side and at least partly removing the dielectric layer on the first side, and at least partly leaving the protection layer in the at least one first trench; and

removing the protection layer from the at least one first trench.

14. The method of claim 13, wherein completely removing the protection layer above the first side and at least partly removing the dielectric layer on the first side includes an etch process that etches the material of the protective layer and the material of the dielectric layer.

15. The method of claim 14, wherein the dielectric layer is an oxide layer, or a nitride layer.

16. The method of claim 14, wherein the protective layer is a resist layer, a carbon layer, or a carbon-containing layer.

17. The method of claim 13, wherein removing the protection layer from the at least one first trench includes an etch process that selectively etches the material of the protect layer.

18. The method of claim 12, further including:

depositing the dielectric layer on the sidewalls in the upper trench section when depositing the dielectric layer on the field plate and on the first side of the semiconductor body;

completely removing the dielectric layer from the first side of the semiconductor body and from the sidewalls of the at least one first trench after removing the protection layer before forming the gate dielectric.

19. The method of claim 12, further including:

forming source and body zones adjacent to the gate dielectric in the semiconductor body after forming the gate electrode.