Recess gate transistor

• US 8,889,539 B2
• Filed: 12/11/2008
• Issued: 11/18/2014
• Est. Priority Date: 04/17/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ryu, Ho-In, Kim, Bong-Su, Kim, Dae-Ik, Lee, Ho-Jun, Jang, Dae-Young, Lee, Si-Hyung
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Liu, Benjamin T
• Application Number:
  US12/332,877
• Publication Number:
  US 20090261420A1
• Time in Patent Office: 2,168 Days
• Field of Search: 257/368, 257/E21.214, 438/589, 438/585, 438/592, 438/259, 438/270, 438/242
• US Class Current: 438/589
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

Claims

1. A method of forming a semiconductor device, comprising:

forming a substrate and an active layer at a top portion of the substrate;

forming a polysilicon layer on the active layer;

forming a first insulation layer on the polysilicon layer;

forming a plurality of masks by patterning the first insulating layer and the polysilicon layer;

forming a plurality of trenches having trench walls in the substrate, each trench disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion;

forming a second insulating layer on the trench walls;

forming a conductive layer on the second insulating layer;

etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches;

depositing a buffer layer on the conductive layer patterns and the trench walls;

filling the upper portions of the trenches with a capping layer;

planarizing the capping layer, the buffer layer, and the hard masks to expose the active layer at the top portion of the substrate;

forming an ILD layer on active layer, the buffer layer, and the capping layer; and

etching the ILD layer above the active layer to form contact holes.

2. The method of claim 1, wherein the etch selectivity from the ILD layer to the capping layer is higher than the etch selectivity from the ILD layer to the buffer layer.