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Recess gate transistor

  • US 8,889,539 B2
  • Filed: 12/11/2008
  • Issued: 11/18/2014
  • Est. Priority Date: 04/17/2008
  • Status: Active Grant
First Claim
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1. A method of forming a semiconductor device, comprising:

  • forming a substrate and an active layer at a top portion of the substrate;

    forming a polysilicon layer on the active layer;

    forming a first insulation layer on the polysilicon layer;

    forming a plurality of masks by patterning the first insulating layer and the polysilicon layer;

    forming a plurality of trenches having trench walls in the substrate, each trench disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion;

    forming a second insulating layer on the trench walls;

    forming a conductive layer on the second insulating layer;

    etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches;

    depositing a buffer layer on the conductive layer patterns and the trench walls;

    filling the upper portions of the trenches with a capping layer;

    planarizing the capping layer, the buffer layer, and the hard masks to expose the active layer at the top portion of the substrate;

    forming an ILD layer on active layer, the buffer layer, and the capping layer; and

    etching the ILD layer above the active layer to form contact holes.

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