Method of fabricating semiconductor device

• US 8,889,543 B2
• Filed: 03/12/2013
• Issued: 11/18/2014
• Est. Priority Date: 04/09/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, Jong-Min, Park, In-Sun, Lee, Jong-Myeong, Hong, Jong-Won, Kim, Hei-Seung, Yoon, Jung-Soo
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US13/795,807
• Publication Number:
  US 20130267088A1
• Time in Patent Office: 616 Days
• Field of Search: 438625-625, 438631-634, 438637-640, 438669-672, 257/E21.587
• US Class Current: 438/625
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming switching devices on a substrate;

forming a lower structure on the substrate having the switching devices;

forming a lower conductive layer on the lower structure;

forming sacrificial mask patterns on the lower conductive layer;

forming lower conductive patterns by etching the lower conductive layer using the sacrificial mask patterns as an etch mask;

forming an interlayer insulating layer on the substrate having the lower conductive patterns;

forming interlayer insulating patterns by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed;

forming openings exposing the lower conductive patterns by removing the exposed sacrificial mask patterns; and

forming upper conductive patterns self-aligned with the lower conductive patterns in the openings.

2. The method according to claim 1, wherein the forming of the interlayer insulating layer comprises forming a layer of insulating material having air spaces therein each located between adjacent ones of the sacrificial mask patterns, and spaced apart from the sacrificial mask patterns.

3. The method according to claim 1, wherein the upper conductive patterns are formed of conductive material having lower resistivity than the lower conductive patterns and to a greater thickness than the lower conductive patterns.

4. The method according to claim 1, wherein the forming of the lower structure comprises forming electrodes, information storage patterns on the electrodes, and an insulating molding pattern surrounding sides of the electrodes and information storage patterns.

5. The method according to claim 4, further comprising forming recesses in an upper surface of the molding pattern by etching the insulating molding pattern using the sacrificial mask patterns as an etch mask, wherein part of the interlayer insulating layer is formed in the recesses.

6. A method of fabricating a semiconductor device, comprising:

forming a lower insulating layer on a substrate;

forming a lower conductive structure form on the lower insulating layer;

forming, on the lower conductive structure, sacrificial mask patterns having a thickness greater than the thickness of the lower conductive structure;

forming lower conductive patterns by etching the lower conductive structure using the sacrificial mask patterns as an etch mask;

forming an interlayer insulating layer on the substrate having the lower conductive patterns;

forming interlayer insulating patterns by planarizing the interlayer insulating layer to such an extent that upper parts of the sacrificial mask patterns are exposed;

forming openings by removing the exposed sacrificial mask patterns; and

forming upper conductive patterns in the openings such that the upper conductive patterns are formed as stacked on the lower conductive patterns, respectively, each of the lower conductive patterns and the upper conductive pattern stacked thereon constituting a respective interconnection structure, and

wherein the interconnection structures are formed to have a thickness greater than the distance between adjacent ones of the interconnection structures.

7. The method according to claim 6, wherein the upper conductive patterns are formed to a thickness greater than the distance between adjacent ones of the interconnection structures.

8. The method according to claim 6, wherein the forming of the interlayer insulating layer comprises forming a layer of insulating material having air spaces therein each located between adjacent ones of the sacrificial mask patterns, and spaced apart from the sacrificial mask patterns.

9. The method according to claim 6, wherein the formation of the upper conductive patterns comprises:

forming a first upper conductive layer covering surfaces delimiting bottoms and sides of the openings;

forming, on the first upper conductive layer, a second upper conductive layer which fills the remainder of the openings and has lower resistivity than the lower conductive patterns; and

planarizing the second upper conductive layer and the first upper conductive layer until upper portions of the interlayer insulating patterns are exposed.

10. The method according to claim 6, further comprising:

forming spacers on surfaces delimiting the sides of the openings.

11. The method according to claim 10, wherein each of the spacers is formed to have an upper portion, and a lower portion whose width is greater than that of the upper portion.

12. The method according to claim 10, wherein each of the sacrificial mask patterns is formed to have an upper portion, and a lower portion whose width is greater than that of the upper portion.

13. The method according to claim 6, further comprising:

forming enlarged openings exposing upper sides of the lower conductive patterns by isotropically etching the interlayer insulating patterns after the sacrificial mask patterns have been removed.

14. The method according to claim 6, further comprising:

forming insulating spacers on sides of the sacrificial mask patterns and lower conductive patterns, after forming the lower conductive patterns.

15. The method according to claim 14, further comprising:

forming capping patterns on the upper conductive patterns,

wherein the upper conductive patterns are formed to fill parts of the openings, respectively, and the capping patterns are formed in what remains of the openings.

16. A method of fabricating a semiconductor device, comprising:

forming a lower conductive structure of at least one layer of material on a substrate;

forming a sacrificial layer on the lower conductive structure, and patterning the sacrificial layer to form lines of sacrificial mask patterns on the lower conductive structure;

etching the at least one layer of material using the sacrificial mask patterns as an etch mask to form lower conductive patterns each having the shape of a line;

forming an interlayer insulating layer on the substrate having the lower conductive patterns;

planarizing the interlayer insulating layer to such an extent that upper parts of the sacrificial mask patterns are exposed and thereby forming interlayer insulating patterns each having the shape of a line from the interlayer insulating layer; and

forming upper conductive patterns as stacked on the lower conductive patterns, respectively, using a damascene process that comprises forming openings having the shapes of lines by removing the exposed sacrificial mask patterns and forming conductive material in the openings, such that each of the lower conductive patterns and the upper conductive pattern stacked thereon constitute a respective interconnection structure having the shape of a line, and

wherein the upper conductive patterns are formed to have a resistivity lower than that of the lower conductive patterns.

17. The method according to claim 16, wherein the interconnection structures are formed to have a thickness greater than the distance between adjacent ones of the interconnection structures.

18. The method according to claim 16, wherein the forming of the upper conductive patterns comprises forming a layer of copper or aluminum in the openings.

19. The method according to claim 16, wherein the forming of the interlayer insulating layer comprises forming a layer of insulating material having air spaces therein each located between adjacent ones of the sacrificial mask patterns, and spaced apart from the sacrificial mask patterns.

20. The method according to claim 16, wherein the upper conductive patterns are formed to each have a width greater than that of the lower conductive pattern on which it is formed.