Semiconductor device and electronic device

• US 8,890,146 B2
• Filed: 02/11/2013
• Issued: 11/18/2014
• Est. Priority Date: 12/11/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kimura, Hajime, Umezaki, Atsushi, Yamazaki, Shunpei
• Primary Examiner(s): Blum, David S
• Application Number:
  US13/763,804
• Publication Number:
  US 20130146882A1
• Time in Patent Office: 645 Days
• Field of Search: 257/57, 257/E27.06
• US Class Current: 257/57
• CPC Class Codes: G02F 1/133302 Rigid substrates, e.g. inorganic substrates
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1334 based on polymer dispersed liquid crystals, e.g. microencapsulated liquid crystals
• CPC Class Codes: G02F 1/13345 Network or three-dimensional gels
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2320/0257 Reduction of after-image effects
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2007 Display of intermediate tones
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/786 : Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 : with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78693 : the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.

Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein a first terminal of the first transistor is electrically connected to a first wiring and a second terminal of the first transistor is electrically connected to a second wiring,

wherein a gate of the second transistor is electrically connected to a third wiring, a first terminal of the second transistor is electrically connected to the third wiring, and a second terminal of the second transistor is electrically connected to a gate of the first transistor,

wherein a gate of the third transistor is electrically connected to a fourth wiring, a first terminal of the third transistor is electrically connected to a fifth wiring, and a second terminal of the third transistor is electrically connected to the second wiring,

wherein a gate of the fourth transistor is electrically connected to the fourth wiring, a first terminal of the fourth transistor is electrically connected to the fifth wiring, and a second terminal of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a channel width of the first transistor is larger than a channel width of the second transistor, and

wherein the second transistor comprises an oxide semiconductor layer comprising a channel formation region.

2. The semiconductor device according to claim 1, the second transistor comprising:

a gate electrode layer on a substrate;

an insulating layer having a layered structure on the gate electrode layer and under and in contact with the oxide semiconductor layer, the insulating layer comprising silicon, oxygen and nitrogen;

a source electrode layer and a drain electrode layer on and in contact with the oxide semiconductor layer, each of the source electrode layer and the drain electrode layer having a layered structure; and

a silicon oxide layer on and in contact with the source electrode layer and the drain electrode layer.

3. The semiconductor device according to claim 1,

wherein an off-state current of the second transistor per channel width of 1 μ

m is 1 aA or less.

4. The semiconductor device according to claim 1,

wherein each of the first transistor, the third transistor and the fourth transistor comprises a separate oxide semiconductor layer.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer includes a non-single-crystal region.

6. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer includes a non-single-crystal region, the non-single-crystal region having a c-axis alignment in a direction perpendicular to a surface of the oxide semiconductor layer.

7. A display device comprising the semiconductor device according to claim 1, and further comprising:

a substrate;

a pixel portion on the substrate;

a gate driver circuit on the substrate, the gate driver circuit being configured to control the pixel portion; and

an input terminal on the substrate,

wherein the semiconductor device is comprised in the gate driver circuit.

8. An electronic device comprising the semiconductor device according to claim 1.

9. A semiconductor device comprising:

a substrate;

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein a first terminal of the first transistor is electrically connected to a first wiring and a second terminal of the first transistor is electrically connected to a second wiring,

wherein a gate of the second transistor is electrically connected to a third wiring, a first terminal of the second transistor is electrically connected to the third wiring, and a second terminal of the second transistor is electrically connected to a gate of the first transistor,

wherein a gate of the third transistor is electrically connected to a fourth wiring, a first terminal of the third transistor is electrically connected to a fifth wiring, and a second terminal of the third transistor is electrically connected to the second wiring,

wherein a gate of the fourth transistor is electrically connected to the fourth wiring, a first terminal of the fourth transistor is electrically connected to the fifth wiring, and a second terminal of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a channel width of the first transistor is larger than a channel width of the second transistor,

wherein the second transistor comprises;

a gate electrode layer on the substrate;

an insulating layer having a layered structure on the gate electrode layer, the insulating layer comprising silicon, oxygen and nitrogen;

an oxide semiconductor layer comprising a channel formation region on and in contact with the insulating layer;

a source electrode layer and a drain electrode layer on and in contact with the oxide semiconductor layer, each of the source electrode layer and the drain electrode layer having a layered structure; and

a silicon oxide layer on and in contact with the oxide semiconductor layer.

10. The semiconductor device according to claim 9, further comprising a silicon nitride layer,

wherein the silicon oxide layer is on and in contact with the source electrode layer and the drain electrode layer, and

wherein the silicon nitride layer is on and in contact with the silicon oxide layer.

11. The semiconductor device according to claim 9,

wherein an off-state current of the second transistor per channel width of 1 μ

m is 1 aA or less.

12. The semiconductor device according to claim 9,

wherein each of the first transistor, the third transistor and the fourth transistor comprises a separate oxide semiconductor layer.

13. The semiconductor device according to claim 9,

wherein the oxide semiconductor layer includes a non-single-crystal region.

14. The semiconductor device according to claim 9,

wherein the oxide semiconductor layer includes a non-single-crystal region, the non-single-crystal region having a c-axis alignment in a direction perpendicular to a surface of the oxide semiconductor layer.

15. A display device comprising the semiconductor device according to claim 9, and further comprising:

a pixel portion on the substrate;

a gate driver circuit on the substrate, the gate driver circuit being configured to control the pixel portion; and

an input terminal on the substrate,

wherein the semiconductor device is comprised in the gate driver circuit.

16. An electronic device comprising the semiconductor device according to claim 9.

17. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein a first terminal of the first transistor is electrically connected to a first wiring and a second terminal of the first transistor is electrically connected to a second wiring,

wherein a gate of the second transistor is electrically connected to a third wiring, a first terminal of the second transistor is electrically connected to the third wiring, and a second terminal of the second transistor is electrically connected to a gate of the first transistor,

wherein a gate of the third transistor is electrically connected to a fourth wiring, a first terminal of the third transistor is electrically connected to a fifth wiring, and a second terminal of the third transistor is electrically connected to the second wiring,

wherein a first terminal of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a channel width of the first transistor is larger than a channel width of the second transistor, and

wherein the second transistor comprises an oxide semiconductor layer comprising a channel formation region.

18. The semiconductor device according to claim 17, the second transistor comprising:

a gate electrode layer on a substrate;

an insulating layer having a layered structure on the gate electrode layer and under and in contact with the oxide semiconductor layer, the insulating layer comprising silicon, oxygen and nitrogen;

a source electrode layer and a drain electrode layer on and in contact with the oxide semiconductor layer, each of the source electrode layer and the drain electrode layer having a layered structure; and

a silicon oxide layer on and in contact with the source electrode layer and the drain electrode layer.

19. The semiconductor device according to claim 17,

wherein an off-state current of the second transistor per channel width of 1 μ

m is 1 aA or less.

20. The semiconductor device according to claim 17,

wherein each of the first transistor, the third transistor and the fourth transistor comprises a separate oxide semiconductor layer.

21. The semiconductor device according to claim 17,

wherein the oxide semiconductor layer includes a non-single-crystal region.

22. The semiconductor device according to claim 17,

wherein the oxide semiconductor layer includes a non-single-crystal region, the non-single-crystal region having a c-axis alignment in a direction perpendicular to a surface of the oxide semiconductor layer.

23. A display device comprising the semiconductor device according to claim 17, and further comprising:

a substrate;

a pixel portion on the substrate;

a gate driver circuit on the substrate, the gate driver circuit being configured to control the pixel portion; and

an input terminal on the substrate,

wherein the semiconductor device is comprised in the gate driver circuit.

24. An electronic device comprising the semiconductor device according to claim 17.