Semiconductor device and manufacturing method thereof

• US 8,890,152 B2
• Filed: 06/13/2012
• Issued: 11/18/2014
• Est. Priority Date: 06/17/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Honda, Tatsuya
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US13/495,313
• Publication Number:
  US 20120319183A1
• Time in Patent Office: 888 Days
• Field of Search: 257/43, 257/59, 257/72, 257/192, 257/291, 257/292, 257/E27.1, 257/E29.117, 257/E29.137
• US Class Current: 257/59
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer.

Claims

1. A semiconductor device comprising:

a first oxide semiconductor layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer provided over the second oxide semiconductor layer to cover side surfaces of the second oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the third oxide semiconductor layer;

a gate insulating film over the source electrode layer and the drain electrode layer; and

a gate electrode layer over the gate insulating film to overlap with the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer,

wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the third oxide semiconductor layer is in contact with part of a top surface of the first oxide semiconductor layer.

3. The semiconductor device according to claim 1,

wherein the first oxide semiconductor layer is formed over and in contact with an oxide insulating film, and

wherein in the oxide insulating film, a thickness of a region in contact with the third oxide semiconductor layer is smaller than a thickness of a region in contact with the first oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer has greater electron affinity than the first oxide semiconductor layer and the third oxide semiconductor layer.

5. The semiconductor device according to claim 1,

wherein the third oxide semiconductor layer covers entirely side surfaces of the second oxide semiconductor layer.

6. The semiconductor device according to claim 1,

wherein the second oxide semiconductor layer comprises In—

Sn—

Zn-based oxide.

7. A semiconductor device comprising:

a first oxide semiconductor layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer provided over the second oxide semiconductor layer to cover side surfaces of the first oxide semiconductor layer and side surfaces of the second oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the third oxide semiconductor layer;

a gate insulating film over the source electrode layer and the drain electrode layer; and

a gate electrode layer over the gate insulating film to overlap with the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer,

wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer.

8. The semiconductor device according to claim 7,

wherein the first oxide semiconductor layer is formed over and in contact with an oxide insulating film, and

wherein in the oxide insulating film, a thickness of a region in contact with the third oxide semiconductor layer is smaller than a thickness of a region in contact with the first oxide semiconductor layer.

9. The semiconductor device according to claim 7, wherein the second oxide semiconductor layer has greater electron affinity than the first oxide semiconductor layer and the third oxide semiconductor layer.

10. The semiconductor device according to claim 7,

wherein the third oxide semiconductor layer covers entirely side surfaces of the first oxide semiconductor layer and entirely side surfaces of the second oxide semiconductor layer.

11. The semiconductor device according to claim 7,

wherein the second oxide semiconductor layer comprises In—

Sn—

Zn-based oxide.

12. A semiconductor device comprising:

a first oxide semiconductor layer;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer provided over the second oxide semiconductor layer to cover side surfaces of the second oxide semiconductor layer;

a gate electrode layer overlapped with the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer; and

a gate insulating film between the gate electrode layer and a stack of the first, second and third oxide semiconductor layers,

wherein the third oxide semiconductor layer comprises indium, gallium, and zinc, and

wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer.

13. The semiconductor device according to claim 12, wherein the third oxide semiconductor layer is in contact with part of a top surface of the first oxide semiconductor layer.

14. The semiconductor device according to claim 12,

wherein the third oxide semiconductor layer covers entirely side surfaces of the second oxide semiconductor layer.

15. The semiconductor device according to claim 12,

wherein the second oxide semiconductor layer comprises In—

Sn—

Zn-based oxide.

16. A semiconductor device comprising:

a first gate electrode;

a gate insulating film over the first gate electrode;

a first oxide semiconductor layer over the gate insulating film;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a third oxide semiconductor layer provided over the second oxide semiconductor layer to cover side surfaces of the second oxide semiconductor layer;

a second gate insulating film over the third oxide semiconductor layer; and

a second gate electrode layer over the second gate insulating film to overlap with the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer,

wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer.

17. The semiconductor device according to claim 16, wherein the third oxide semiconductor layer is in contact with part of a top surface of the first oxide semiconductor layer.

18. The semiconductor device according to claim 16,

wherein the third oxide semiconductor layer covers entirely side surfaces of the second oxide semiconductor layer.

19. The semiconductor device according to claim 16,

wherein the second oxide semiconductor layer comprises In—

Sn—

Zn-based oxide.