Chip package and method for forming the same
First Claim
1. A chip package, comprising:
- a substrate having a first surface and a second surface;
an optoelectronic device formed in the substrate;
a through-hole extending from the second surface to the first surface;
a conducting layer disposed on the substrate;
an insulating layer disposed between the substrate and the conducting layer;
a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer, and wherein there is no solder resist material contacting with the conducting layer and the light shielding layer on the second surface; and
a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate,wherein the through-hole is partially filled with the light shielding layer such that a void is formed between a bottom of the through-hole and the light shielding layer in the through-hole, and wherein a portion of the conducting layer, which overlies both sidewalls and the bottom of the through-hole, directly contacts the void.
1 Assignment
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Accused Products
Abstract
An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate.
17 Citations
16 Claims
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1. A chip package, comprising:
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a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a through-hole extending from the second surface to the first surface; a conducting layer disposed on the substrate; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer, and wherein there is no solder resist material contacting with the conducting layer and the light shielding layer on the second surface; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate, wherein the through-hole is partially filled with the light shielding layer such that a void is formed between a bottom of the through-hole and the light shielding layer in the through-hole, and wherein a portion of the conducting layer, which overlies both sidewalls and the bottom of the through-hole, directly contacts the void. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for forming a chip package, comprising:
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providing a substrate having a first surface and a second surface, wherein at least an optoelectronic device is formed in the substrate; forming a through-hole extending from the second surface to the first surface; forming an insulating layer on the substrate; forming a conducting layer on the insulating layer on the substrate, wherein the conducting layer is electrically connected to the at least an optoelectronic device; forming a light shielding layer on the second surface of the substrate, wherein the light shielding layer directly contacts with the conducting layer and has at least an opening exposing the conducting layer, and the light shielding layer has a light shielding rate of more than about 80%, and wherein there is no solder resist material contacting with the conducting layer and the light shielding layer on the second surface; and forming a conducting bump in the at least an opening of the light shielding layer to electrically connect to the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate, wherein the through-hole is partially filled with the light shielding layer such that a void is formed between a bottom of the through-hole and the light shielding layer in the through-hole, and wherein a portion of the conducting layer, which overlies both sidewalls and the bottom of the through-hole, directly contacts the void. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification