Methods and apparatus for non-volatile memory cells with increased programming efficiency

• US 8,890,232 B2
• Filed: 02/10/2014
• Issued: 11/18/2014
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsair, Yong-Shiuan, Chu, Wen-Ting, Liu, Po-Wei, Huang, Wen-Tuo, Yang, Yu-Hsiang, Chiu, Chieh-Fei, Hsu, Yu-Ling
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US14/176,968
• Publication Number:
  US 20140151782A1
• Time in Patent Office: 281 Days
• Field of Search: 257/316, 257/E29.129, 257/E29.3, 438/257
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

Claims

1. An method comprising:

providing a substrate;

forming a floating gate layer over the substrate and a control gate over the floating gate layer, the floating gate layer having a first portion extending past a first side of the control gate and a second portion extending past a second side of the control gate;

forming a first dielectric layer over a first sidewall and a second sidewall of the control gate and over the floating gate layer on the first side and the second side of the control gate;

removing a first horizontal portion of the first dielectric layer extending over the first portion of the floating gate layer, a second horizontal portion of the first dielectric layer extending over the second portion of the floating gate layer remaining;

after the removing, forming a second dielectric layer over the first dielectric layer along the first sidewall and the second sidewall of the control gate, the second dielectric layer directly contacting an upper surface of the first portion of the floating gate layer, the first dielectric layer completely separating the second dielectric layer from the upper surface of the second portion of the floating gate layer; and

after the forming the second dielectric layer, patterning the floating gate layer on the first side and the second side of the control gate to form a floating gate.

2. The method of claim 1, wherein the first dielectric layer forms an L-shaped liner along the second side of the control gate.

3. The method of claim 1, further comprising forming an erase gate extending over at least a portion of the floating gate.

4. The method of claim 3, wherein the erase gate overlies at least 5 percent of the floating gate.

5. The method of claim 3, wherein the erase gate overlies between 5 and 20 percent of the floating gate.

6. The method of claim 3, wherein the erase gate overlies between 5 and 10 percent of the upper surface of the floating gate.

7. A method comprising:

forming a floating gate layer over a semiconductor substrate and a control gate layer over the floating gate layer;

patterning the control gate layer, thereby forming a control gate having a first sidewall on a first side and a second sidewall on a second side;

forming a first dielectric layer over the first sidewall and the second sidewall of the control gate;

patterning the first dielectric layer along the first sidewall such that the first dielectric layer is discontinuous with the first dielectric layer along the second sidewall;

after the patterning the first dielectric layer, forming a second dielectric layer over the first dielectric layer along the first sidewall and the second sidewall;

patterning the second dielectric layer along the first sidewall and the second sidewall, the second dielectric layer being in direct contact with the floating gate layer on the first side of the control gate, the first dielectric layer being interposed between the second dielectric layer and the floating gate layer on the second side of the control gate;

patterning the floating gate layer using the first dielectric layer and the second dielectric layer as a mask, thereby forming a floating gate having a first side and a second side, the first dielectric layer and the second dielectric layer being used as a mask to pattern both the first side and the second side of the floating gate;

removing the second dielectric layer along the first sidewall; and

forming an erase gate along the first sidewall, the erase gate overlying at least a portion of the floating gate.

8. The method of claim 7, further comprising masking the second dielectric layer along the second sidewall prior to the removing the second dielectric layer along the first sidewall, such that the second dielectric layer along the second sidewall remains.

9. The method of claim 7, after the patterning the floating gate, further comprising forming a third dielectric layer over the second dielectric layer.

10. The method of claim 9, patterning the third dielectric layer, thereby exposing the semiconductor substrate in a common source region on a first side of the floating gate.

11. The method of claim 7, wherein the forming the erase gate comprises forming a third dielectric layer over an exposed portion of the floating gate on the first side of the control gate, and forming the erase gate over the third dielectric layer.

12. The method of claim 7, wherein the erase gate overlies at least 5 percent of the floating gate.

13. The method of claim 7, wherein the erase gate overlies between 5 and 20 percent of the floating gate.

14. The method of claim 7, wherein the erase gate overlies between 5 and 10 percent of the floating gate.

15. An apparatus comprising:

a substrate;

a floating gate over the substrate;

a control gate over the floating gate, the floating gate having a first portion extending past a first side of the control gate and a second portion extending past a second side of the control gate;

a first dielectric layer extending over a first sidewall and a second sidewall of the control gate, the first dielectric layer completely covering an upper surface of the second portion of the floating gate, the first dielectric layer having an L-shape over the second portion of the floating gate, the first dielectric layer not having an L-shape over the first portion of the floating gate;

a second dielectric layer over the first dielectric layer, the second dielectric layer directly contacting an upper surface of the first portion of the floating gate; and

a third dielectric layer over the first dielectric layer over the second portion, the first dielectric layer completely separating the third dielectric layer from the upper surface of the second portion of the floating gate.

16. The apparatus of claim 15, further comprising an erase gate, the erase gate extending over the first portion of the floating gate.

17. The apparatus of claim 16, further comprising a common source in the substrate below the erase gate.

18. The apparatus of claim 16, wherein the erase gate overlying at least a portion of the upper surface of the floating gate covers at least 5 percent of the upper surface of the floating gate.

19. The apparatus of claim 16, wherein the erase gate overlying at least a portion of the upper surface of the floating gate covers between 5 and 20 percent of the upper surface of the floating gate.

20. The apparatus of claim 16, wherein the erase gate overlying at least a portion of the upper surface of the floating gate covers between 5 and 10 percent of the upper surface of the floating gate.