Methods and apparatus for non-volatile memory cells with increased programming efficiency
First Claim
1. An method comprising:
- providing a substrate;
forming a floating gate layer over the substrate and a control gate over the floating gate layer, the floating gate layer having a first portion extending past a first side of the control gate and a second portion extending past a second side of the control gate;
forming a first dielectric layer over a first sidewall and a second sidewall of the control gate and over the floating gate layer on the first side and the second side of the control gate;
removing a first horizontal portion of the first dielectric layer extending over the first portion of the floating gate layer, a second horizontal portion of the first dielectric layer extending over the second portion of the floating gate layer remaining;
after the removing, forming a second dielectric layer over the first dielectric layer along the first sidewall and the second sidewall of the control gate, the second dielectric layer directly contacting an upper surface of the first portion of the floating gate layer, the first dielectric layer completely separating the second dielectric layer from the upper surface of the second portion of the floating gate layer; and
after the forming the second dielectric layer, patterning the floating gate layer on the first side and the second side of the control gate to form a floating gate.
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Abstract
Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.
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Citations
20 Claims
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1. An method comprising:
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providing a substrate; forming a floating gate layer over the substrate and a control gate over the floating gate layer, the floating gate layer having a first portion extending past a first side of the control gate and a second portion extending past a second side of the control gate; forming a first dielectric layer over a first sidewall and a second sidewall of the control gate and over the floating gate layer on the first side and the second side of the control gate; removing a first horizontal portion of the first dielectric layer extending over the first portion of the floating gate layer, a second horizontal portion of the first dielectric layer extending over the second portion of the floating gate layer remaining; after the removing, forming a second dielectric layer over the first dielectric layer along the first sidewall and the second sidewall of the control gate, the second dielectric layer directly contacting an upper surface of the first portion of the floating gate layer, the first dielectric layer completely separating the second dielectric layer from the upper surface of the second portion of the floating gate layer; and after the forming the second dielectric layer, patterning the floating gate layer on the first side and the second side of the control gate to form a floating gate. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising:
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forming a floating gate layer over a semiconductor substrate and a control gate layer over the floating gate layer; patterning the control gate layer, thereby forming a control gate having a first sidewall on a first side and a second sidewall on a second side; forming a first dielectric layer over the first sidewall and the second sidewall of the control gate; patterning the first dielectric layer along the first sidewall such that the first dielectric layer is discontinuous with the first dielectric layer along the second sidewall; after the patterning the first dielectric layer, forming a second dielectric layer over the first dielectric layer along the first sidewall and the second sidewall; patterning the second dielectric layer along the first sidewall and the second sidewall, the second dielectric layer being in direct contact with the floating gate layer on the first side of the control gate, the first dielectric layer being interposed between the second dielectric layer and the floating gate layer on the second side of the control gate; patterning the floating gate layer using the first dielectric layer and the second dielectric layer as a mask, thereby forming a floating gate having a first side and a second side, the first dielectric layer and the second dielectric layer being used as a mask to pattern both the first side and the second side of the floating gate; removing the second dielectric layer along the first sidewall; and forming an erase gate along the first sidewall, the erase gate overlying at least a portion of the floating gate. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. An apparatus comprising:
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a substrate; a floating gate over the substrate; a control gate over the floating gate, the floating gate having a first portion extending past a first side of the control gate and a second portion extending past a second side of the control gate; a first dielectric layer extending over a first sidewall and a second sidewall of the control gate, the first dielectric layer completely covering an upper surface of the second portion of the floating gate, the first dielectric layer having an L-shape over the second portion of the floating gate, the first dielectric layer not having an L-shape over the first portion of the floating gate; a second dielectric layer over the first dielectric layer, the second dielectric layer directly contacting an upper surface of the first portion of the floating gate; and a third dielectric layer over the first dielectric layer over the second portion, the first dielectric layer completely separating the third dielectric layer from the upper surface of the second portion of the floating gate. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification