3D memory array with improved SSL and BL contact layout

• US 8,890,233 B2
• Filed: 01/31/2011
• Issued: 11/18/2014
• Est. Priority Date: 07/06/2010
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hung, Chun-Hsiung, Lue, Hang-Ting, Shen, Shin-Jang
• Primary Examiner(s): FERNANDES, ERROL V
• Application Number:
  US13/018,110
• Publication Number:
  US 20120007167A1
• Time in Patent Office: 1,387 Days
• Field of Search: 257/211, 257/288, 257/314, 257/324, 257/329, 257/774, 438/102, 438/104, 438/128
• US Class Current: 257/324
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays

Abstract

A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines.

Claims

1. A memory device, comprising:

an integrated circuit substrate;

a plurality of stacks of semiconductor material strips extending out of the integrated circuit substrate, the plurality of stacks including at least two semiconductor material strips separated by insulating material into different plane positions of a plurality of plane positions, different stacks of the plurality of stacks sharing a same staircase-shaped structure, the semiconductor material strips that share a same plane position of the plurality of plane positions being electrically coupled to a same bit line of a plurality of bit lines;

the plurality of bit lines electrically coupled via a first plurality of conducting plugs to the plurality of stacks at the plurality of different plane positions, such that different bit lines distinguish different plane positions of the plurality of plane positions;

a plurality of column select lines electrically coupled via a second plurality of conducting plugs to the plurality of stacks at the plurality of different plane positions, such that different column select lines of the plurality of column select lines distinguish different stacks of the plurality of stacks;

wherein the first plurality of conducting plugs and the second plurality of conducting plugs electrically couple to the plurality of stacks at different locations along the plurality of stacks;

a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the semiconductor material strips and the plurality of conductive lines, wherein the plurality of conductive lines arranged across the plurality of stacks; and

memory elements in the interface regions, which establish a 3D array of memory cells accessible via the plurality of semiconductor material strips and the plurality of conductive lines.

2. The memory device of claim 1, including

decoding circuits coupled to the semiconductor material strips in the plurality of stacks and to the plurality of conductive lines for accessing the memory cells.

3. The memory device of claim 1, wherein the memory elements comprise an anti-fuse.

4. The memory device of claim 1, wherein the memory elements comprise a charge storage structure.

5. The memory device of claim 1, wherein the memory cells comprise buried channel charge storage transistors.

6. The memory device of claim 1, wherein the plurality of semiconductor material strips in the plurality of stacks comprise a doped semiconductor.

7. The memory device of claim 1, wherein the plurality of conductive lines comprise a doped semiconductor.

8. The memory device of claim 1, wherein said memory elements comprise portions of a common layer of memory material between the plurality of conductive lines and the plurality of stacks.

9. The memory device of claim 1, including a tunneling layer, a charge trapping layer and a blocking layer between the plurality of conductive lines and the plurality of stacks, and wherein said tunneling layer, charge trapping layer and blocking layer, in combination, form said memory elements in said interface regions.

10. A method for manufacturing a memory device, comprising:

forming a plurality of stacks of semiconductor material strips extending out of an integrated circuit substrate, the plurality of stacks including at least two semiconductor material strips separated by insulating material into different plane positions of a plurality of plane positions, different stacks of the plurality of stacks sharing a same staircase-shaped structure, the semiconductor material strips that share a same plane position of the plurality of plane positions being electrically coupled to a same bit line of a plurality of bit lines;

forming the plurality of bit lines electrically coupled via a first plurality of conducting plugs to the plurality of stacks at the plurality of different plane positions, such that different bit lines distinguish different plane positions of the plurality of plane positions;

forming a plurality of column select lines electrically coupled via a second plurality of conducting plugs to the plurality of stacks at the plurality of different plane positions, such that different column select lines of the plurality of column select lines distinguish different stacks of the plurality of stacks;

wherein the first plurality of conducting plugs and the second plurality of conducting plugs electrically couple to the plurality of stacks at different locations along the plurality of stacks;

forming a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the semiconductor material strips and the plurality of conductive lines wherein the plurality of conductive lines arranged across the plurality of stacks; and

forming memory elements in the interface regions, which establish a 3D array of memory cells accessible via the plurality of semiconductor material strips and the plurality of conductive lines.