Power semiconductor devices, structures, and related methods
First Claim
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1. A semiconductor device, comprising:
- an n-type semiconductor source region;
a p-type semiconductor body region;
a gate electrode, which is capacitively coupled to invert a portion of said body region;
a semiconductor drift region which includes both n-type and p-type semiconductor portions electrically connected in parallel;
immobile positive point charges which are capacitively coupled to jointly invert parts of said p-type drift region portions; and
an n-type semiconductor drain region;
wherein said body region is interposed between said source region and said drift region;
and wherein said drift region is interposed between said body region and said drain region;
whereby, in the ON state, electrons flow both through said n-type portions and said p-type portions of said drift region in parallel.
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Abstract
Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
3 Citations
20 Claims
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1. A semiconductor device, comprising:
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an n-type semiconductor source region; a p-type semiconductor body region; a gate electrode, which is capacitively coupled to invert a portion of said body region; a semiconductor drift region which includes both n-type and p-type semiconductor portions electrically connected in parallel; immobile positive point charges which are capacitively coupled to jointly invert parts of said p-type drift region portions; and an n-type semiconductor drain region; wherein said body region is interposed between said source region and said drift region; and wherein said drift region is interposed between said body region and said drain region; whereby, in the ON state, electrons flow both through said n-type portions and said p-type portions of said drift region in parallel. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device, comprising:
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a first-conductivity-type semiconductor source region; a second-conductivity-type semiconductor body region; a generally planar gate electrode, which is capacitively coupled to invert a portion of said body region to define a predominantly horizontal channel therein; a semiconductor drift region which includes both first-conductivity-type and second-conductivity-type semiconductor pillars in parallel; immobile electrostatic charge which is capacitively coupled to invert parts of said second-conductivity-type drift region portions; and a first-conductivity-type semiconductor drain region; wherein said body region is interposed between said source region and said drift region; and wherein said drift region is interposed between said body region and said drain region; and wherein, in the ON state, majority carriers flow both through said first-conductivity-type and said second-conductivity-type pillars in parallel. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A semiconductor device, comprising:
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an n-type semiconductor source region; a p-type semiconductor body region; a planar gate electrode, which is capacitively coupled to invert a portion of said body region to define a predominantly horizontal channel therein; a semiconductor drift region which includes both n-type and p-type semiconductor pillars in parallel; immobile electrostatic charge which is capacitively coupled to invert parts of said p-type drift region portions; and an n-type semiconductor drain region; wherein said body region is interposed between said source region and said drift region; and wherein said drift region is interposed between said body region and said drain region; and wherein, in the ON state, majority carriers flow both through said n-type and said p-type pillars in parallel. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification