Discrete three-dimensional memory comprising off-die read/write-voltage generator

• US 8,890,300 B2
• Filed: 03/06/2013
• Issued: 11/18/2014
• Est. Priority Date: 09/01/2011
• Status: Expired due to Fees

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Mehta, Ratisha
• Application Number:
  US13/787,787
• Publication Number:
  US 20130188415A1
• Time in Patent Office: 622 Days
• Field of Search: 257/296, 257/303, 257/311, 257/314, 257/315, 257/686, 438/238, 438/241, 438/257, 438/258, 438/262, 438/264, 438/266
• US Class Current: 257/686
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (V_R/V_W-generator) is located on a separate peripheral-circuit die. The V_R/V_W-generator generates at least a read and/or write voltage to the 3D-array die. A single V_R/V_W-generator die can support multiple 3D-array dies.

Claims

1. A discrete three-dimensional memory (3D-M), comprising:

a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels;

a peripheral-circuit die comprising at least a portion of a read/write-voltage generator for providing said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;

wherein said portion of said read/write-voltage generator is absent from said 3D-array die;

said peripheral-circuit die comprises fewer back-end layers than said 3D-array die, and said 3D-array die and said peripheral-circuit die are separate dice.

2. The discrete 3D-M according to claim 1, wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

3. The discrete 3D-M according to claim 1, wherein said 3D-M comprises at least one of a memristor, a resistive random-access memory (RRAM or ReRAM), a phase-change memory, a programmable metallization cell (PMC), and a conductive-bridging random-access memory (CBRAM).

4. The discrete 3D-M according to claim 1, wherein said read/write-voltage generator comprises a step-up whose output voltage is higher than the voltage supply.

5. The discrete 3D-M according to claim 4, wherein said step-up comprises at least one of a charge pump and a boost converter.

6. The discrete 3D-M according to claim 1, wherein said read/write-voltage generator comprises a step-down whose output voltage is lower than the voltage supply.

7. The discrete 3D-M according to claim 6, wherein said step-down comprises at least one of a low dropout and a buck converter.

8. The discrete 3D-M according to claim 1, further comprising another 3D-M die, wherein said peripheral-circuit die further comprises at least another portion of another read/write-voltage generator for said another 3D-M die, and said another portion of said another read/write-voltage generator is absent from said another 3D-M die.

9. The discrete 3D-M according to claim 1, wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card or a solid-state drive.

10. The discrete 3D-M according to claim 1, wherein the array efficiency of said 3D-array die is larger than 40%.

11. A discrete three-dimensional memory (3D-M), comprising:

a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels;

a peripheral-circuit die comprising at least a portion of a read/write-voltage generator for providing said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;

wherein said portion of said read/write-voltage generator is absent from said 3D-array die;

said peripheral-circuit die comprises different interconnect materials than said 3D-array die, and said 3D-array die and said peripheral-circuit die are separate dice.

12. The discrete 3D-M according to claim 11, wherein 3D-array die comprises high-temperature interconnect materials.

13. The discrete 3D-M according to claim 11, wherein peripheral-circuit die comprises high-speed interconnect materials.

14. The discrete 3D-M according to claim 11, wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

15. The discrete 3D-M according to claim 11, further comprising another 3D-M die, wherein said peripheral-circuit die further comprises at least another portion of another read/write-voltage generator for said another 3D-M die, and said another portion of said another read/write-voltage generator is absent from said another 3D-M die.

16. The discrete 3D-M according to claim 11, wherein the array efficiency of said 3D-array die is larger than 40%.

17. A discrete three-dimensional memory (3D-M), comprising:

a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory levels;

a peripheral-circuit die comprising at least a portion of a read/write-voltage generator for providing said 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;

wherein said portion of said read/write-voltage generator is absent from said 3D-array die;

said peripheral-circuit die comprises more substrate interconnect layers than said 3D-array die, and said 3D-array die and said peripheral-circuit die are separate dice.

18. The discrete 3D-M according to claim 17, wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

19. The discrete 3D-M according to claim 17, further comprising another 3D-M die, wherein said peripheral-circuit die further comprises at least another portion of another read/write-voltage generator for said another 3D-M die, and said another portion of said another read/write-voltage generator is absent from said another 3D-M die.

20. The discrete 3D-M according to claim 17, wherein the array efficiency of said 3D-array die is larger than 40%.