Systems and methods for frequency synthesis to improve coexistence

• US 8,890,625 B2
• Filed: 01/03/2013
• Issued: 11/18/2014
• Est. Priority Date: 01/03/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chang, Richard, O'Sullivan, Tomas, Marcu, Cristian, Kaczynski, Brian
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US13/733,746
• Publication Number:
  US 20140184342A1
• Time in Patent Office: 684 Days
• Field of Search: 331/16, 331/34, 331/177.R, 331/179, 375/376, 455/260, 332/127
• US Class Current: 331/1.A
• CPC Class Codes: H03B 21/02 by plural beating, i.e. for frequency synthesis ; Beating in combination with multiplication or division of frequency digital frequency synthesis using a ROM G06F1/02; digital frequency synthesis in general H03K; indirect frequency synthesis using a PLL H03L7/16
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A frequency synthesizer for a WLAN transceiver is disclosed that may be used to generate 5.4 GHz and 2.4 GHz signals. The frequency synthesizer may be configured to minimize VCO pulling by using VCO operating frequencies that are not integer multiples of the RF bands. Further, the frequency synthesizer may be configured to minimize interference with other frequency bands used by existing wireless systems.

Claims

1. A frequency synthesizer, comprising:

a first voltage controlled oscillator (VCO) to generate a signal having a first frequency;

a first mixer coupled to the first VCO;

a first divide block, coupled to the first VCO and the first mixer to output a first feedback signal for controlling the first VCO, and

a divided signal to the first mixer;

a second VCO to generate a signal having a second frequency and to output a second feed back signal for controlling the second VCO;

a second mixer coupled to the second VCO; and

a second divide block, coupled to the second VCO and the second mixer, to output a divided signal to the second mixer;

wherein the first VCO to output the signal having the first frequency to the first divide block and to the first mixer,

the first mixer to generate a first synthesized signal having a frequency that is a non-integer multiple of the first frequency, comprising combining the divided signal from the first divide block with the signal having the first frequency,

the second VCO to output the signal having the second frequency to the second divide block and to the second mixer, and

the second mixer to generate a second synthesized signal having a frequency that is a non-integer multiple of the second frequency, comprising combining the divided signal from the second divide block with the signal having the second frequency.

2. The frequency synthesizer of claim 1, further comprising:

a first quadrature divide by two block coupled to the first mixer, to;

receive the first synthesized signal from the first mixer, and

generate using the first synthesized signal;

a first in-phase (I) local oscillator signal at one-half the frequency of the first synthesized signal; and

a first quadrature (Q) local oscillator signal at one-half the frequency of the first synthesized signal; and

a second quadrature divide by two block, coupled to the second mixer, to;

receive the second synthesized signal from the second mixer, and

generate using the second synthesized signal;

a second I local oscillator signal at one-half the frequency of the second synthesized signal, and

a second Q local oscillator signal at one-half the frequency of the second synthesized signal.

3. The frequency synthesizer of claim 2, wherein the first and second divide blocks comprise divide by three blocks.

4. The frequency synthesizer of claim 3, wherein the first I and Q local oscillator signals each have a frequency ⅔

of the first frequency and wherein the second I and Q local oscillator signals each have a frequency ⅔

of the second frequency.

5. The frequency synthesizer of claim 4, wherein the first frequency is in the range of approximately 7.35 GHz to 8.74 GHz and wherein the second frequency is in the range of approximately 3.6 GHz to 3.72525 GHz.

6. The frequency synthesizer of claim 1, further comprising a common regulatory path.

7. The frequency synthesizer of claim 6, wherein the common regulatory path to receive the first feed back signal from the first divide block and the second feed back signal from the second VCO.

8. The frequency synthesizer of claim 1, wherein the second VCO to exhibit less phase noise than the first VCO.

9. The frequency synthesizer of claim 8, wherein the first VCO has a first inductance and the second VCO has a second inductance, such that the second inductance is less than the first inductance.

10. A method for synthesizing frequencies comprising:

generating a first signal having a first frequency with a first voltage controlled oscillator (VCO);

dividing the first signal with a first divide block to create a first divided signal;

outputting a first feed back signal from the first divide block for controlling the first VCO;

mixing the first signal with the first divided signal to generate a first synthesized signal having a frequency that is a non-integer multiple of the first frequency;

generating a second signal having a second frequency with a second VCO;

outputting a second feed back signal from the second VCO for controlling the second VCO;

dividing the second signal with a second divide block to create a second divided signal; and

mixing the second signal with the second divided signal to generate a second synthesized signal having a frequency that is a non-integer multiple of the second frequency.

11. The method of claim 10, further comprising:

dividing the first synthesized signal with a first quadrature divide by two block to generate a first in-phase (I) local oscillator signal at one-half the frequency of the first synthesized signal and a first quadrature (Q) local oscillator signal at one-half the frequency of the first synthesized signal; and

dividing the second synthesized signal with a second quadrature divide by two block to generate a second I local oscillator signal at one-half the frequency of the second synthesized signal and a second quadrature Q local oscillator signal at one-half the frequency of the second synthesized signal.

12. The method of claim 11, wherein dividing the first signal with the first divide block comprises dividing by three and dividing the second signal with the second divide block comprises dividing by three.

13. The method of claim 12, wherein dividing the first synthesized signal with the first quadrature divide by two block generates first I and Q local oscillator signals at ⅔

of the frequency of the first signal and dividing the second synthesized signal with the second quadrature divide by two block generates second I and Q local oscillator signals at ⅔

of the frequency of the second signal.

14. The method of claim 13, wherein the first frequency is in the range of approximately 7.35 GHz to 8.74 GHz and wherein the second frequency is in the range of approximately 3.6 GHz to 3.72525 GHz.

15. The method of claim 10, further comprising controlling the first and second VCOs with a common regulatory path.

16. The method of claim 15, further comprising taking the first feed back signal for the common regulatory path from the first divide block and taking the second feed back signal for the common regulatory path from the second VCO.

17. The method of claim 10, wherein the second VCO exhibits less phase noise than the first VCO.

18. The method of claim 17, wherein the first VCO has a first inductance and the second VCO has a second inductance, such that the second inductance is less than the first inductance.