Divider-less phase locked loop (PLL)

• US 8,890,626 B2
• Filed: 08/15/2012
• Issued: 11/18/2014
• Est. Priority Date: 08/15/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Yen-Jen, Lee, I-Ting, Hsieh, Hsieh-Hung, Jou, Chewn-Pu, Hsueh, Fu-Lung, Liu, Shen-Iuan
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US13/586,033
• Publication Number:
  US 20140049329A1
• Time in Patent Office: 825 Days
• Field of Search: 331/16, 331/34, 331/17, 331/57, 327/156, 327/159
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03L 7/083 the reference signal being additionally directly applied to the generator
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulse_PD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulse_PD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulse_PD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

Claims

1. A method for phase detection within a divider-less phase locked loop (PLL), comprising:

receiving a pulse phase detector (pulse_PD) signal associated with a reference frequency;

receiving a voltage controlled oscillator positive differential (VCOP) signal and a voltage controlled oscillator negative differential (VCON) signal, the VCOP signal and the VCON signal corresponding to a differential pair associated with an output frequency of a voltage controlled oscillator (VCO);

generating a first up signal and a first down signal for a first charge pump (CP), at least one of the first up signal or the first down signal based on the pulse_PD signal and at least one the first up signal or the first down signal based on the VCOP signal; and

generating a second up signal and a second down signal for a second CP, at least one of the second up signal or the second down signal based on the pulse_PD signal and at least one of the second up signal or the second down signal based on the VCON signal.

2. The method of claim 1, comprising generating at least one of the first up signal, the first down signal, the second up signal, or the second down signal such that a zero crossing of the VCON signal and the VCOP signal is substantially centered with respect to the pulse_PD signal.

3. The method of claim 1, comprising generating at least one of the first up signal, the first down signal, the second up signal, or the second down signal such that a phase difference between the pulse_PD signal and a zero crossing of the VCON signal and the VCOP signal is zero.

4. The method of claim 1, comprising disconnecting a divider from at least one of the VCON signal or VCOP signal in response to a lock in a phase locked loop (PLL).

5. The method of claim 1, comprising enabling a pulse injection associated with the VCO in response to an adjustment to a zero crossing phase of the VCON signal and the VCOP signal.

6. The method of claim 1, comprising generating at least one of:

a first signal comprising a logical AND of the VCOP signal and the pulse_PD signal;

or

a second signal comprising a logical AND of the VCON signal and the pulse_PD signal.

7. The method of claim 6, comprising controlling a pulse width for the first signal based on at least one of a delay or an OR gate.

8. The method of claim 1, at least one of:

the generating a first up signal comprising generating a rising edge of the first up signal based on a rising edge of the pulse_PD signal;

or

the generating a second up signal comprising generating a rising edge of the second up signal based on a falling edge of the pulse_PD signal.

9. The method of claim 1, at least one of:

the generating a first down signal comprising generating a rising edge of the first down signal based on a rising edge of the VCOP signal;

or

the generating a second down signal comprising generating a rising edge of the second down signal based on a falling edge of the VCON signal.

19. The method of claim 1, the generating a first down signal comprising generating an edge of the first down signal based on an edge of the VCOP signal.

20. The method of claim 1, the first up signal different than the second up signal.

10. A phase detector (PD) for a divider-less phase locked loop (PLL), configured to:

receive a pulse phase detector (pulse_PD) signal associated with a reference frequency;

receive a voltage controlled oscillator positive differential (VCOP) signal and a voltage controlled oscillator negative differential (VCON) signal, at least one of the VCOP signal or the VCON signal associated with an output frequency of a voltage controlled oscillator (VCO), the output frequency of the VCO comprising an integer multiple of the reference frequency; and

generate at least one of a first up signal for a first charge pump (CP), a first down signal for the first CP, a second up signal for a second CP, or a second down signal for the second CP based on at least one of the pulse_PD signal, the VCOP signal, or the VCON signal, at least one of the first up signal, the first down signal, the second up signal, or the second down signal configured to adjust a zero crossing phase of the VCON signal and the VCOP signal with respect to the pulse_PD signal.

11. The phase detector (PD) of claim 10, configured to generate at least one of:

a first signal comprising a logical AND of the VCOP signal and the pulse_PD signal;

or

a second signal comprising a logical AND of the VCON signal and the pulse_PD signal.

12. The phase detector (PD) of claim 11, configured to control a pulse width for the first signal based on at least one of a delay or an OR gate.

13. The phase detector (PD) of claim 10, configured to generate at least one of:

a rising edge of the first up signal based on a rising edge of the pulse_PD signal;

or

a rising edge of the second up signal based on a falling edge of the pulse_PD signal.

14. The phase detector (PD) of claim 10, configured to generate at least one of:

a rising edge of the first down signal based on a rising edge of the VCOP signal;

or

a rising edge of the second down signal based on a falling edge of the VCON signal.

15. A divider-less phase locked loop (PLL), comprising:

a pulse generator configured to generate a pulse phase detector (pulse_PD) signal based on a reference frequency;

a phase detector (PD) configured to;

generate a first up signal and a first down signal, at least one of the first up signal or the first down signal generated based on a voltage controlled oscillator positive differential (VCOP) signal, and

generate a second up signal and a second down signal, at least one of second up signal or the second down signal generated based on a voltage controlled oscillator negative differential (VCON) signal;

a first charge pump (CP) configured to generate a first portion of an output CP signal based on at least one of the first up signal or the first down signal;

a second CP configured to generate a second portion of the output CP signal based on at least one of the second up signal or the second down signal;

a voltage controlled oscillator (VCO) configured to generate the VCOP signal and the VCON signal based on output CP signal.

16. The divider-less phase locked loop (PLL) of claim 15, at least one of the PD, the first CP, or the second CP configured to control a charge ratio between the first CP and the second CP.

17. The divider-less phase locked loop (PLL) of claim 15, at least one of the PD, the first CP, or the second CP configured to adjust a zero crossing phase of the VCON signal and the VCOP signal with respect to the pulse_PD signal.

18. The divider-less phase locked loop (PLL) of claim 15, the pulse generator configured to inject a pulse injection signal into the VCO based on a phase difference between the pulse_PD signal and a zero crossing of the VCON signal and the VCOP signal.