Oscillator apparatus and method with wide adjustable frequency range

• US 8,890,630 B2
• Filed: 07/18/2011
• Issued: 11/18/2014
• Est. Priority Date: 07/18/2011
• Status: Active Grant

• Current Assignee: Crane Electronics, Inc. (Crane Company)
• Original Assignee: Crane Electronics, Inc. (Crane Company)
• Inventors: Hughes, Rodney Alan
• Primary Examiner(s): Kinkead, Arnold
• Assistant Examiner(s): Tan, Richard
• Application Number:
  US13/185,152
• Publication Number:
  US 20130021108A1
• Time in Patent Office: 1,219 Days
• Field of Search: 331/108.D, 331/108.R, 331/111, 331/143, 331/145, 331/149, 331/153
• US Class Current: 331/143
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H03B 2200/0074 Locking of an oscillator by injecting an input signal directly into the oscillator
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/24 active element in amplifier being semiconductor device H03B5/26 takes precedence
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03K 4/12 in which a sawtooth voltage is produced across a capacitor

Abstract

An oscillator formed from low cost discrete semiconductors and passive devices creates a linear periodic ramp of constant frequency with ramp slope based on an external voltage signal. Parameters are stable over a wide range of temperatures and variations of transistor parameters that normally degrade in extreme environments. The oscillator period can be phase and frequency synchronized to an external clock source over a wide range of frequencies. The oscillator ramp generator phase can be synchronized on a cycle by cycle basis for incorporation in power converters employing spread spectral EMI reduction techniques, multi-converter systems employing clock interleaving for distribution bus filter optimization, and resonant mode converters employing zero voltage switching techniques. Oscillator ramp rate is independent of frequency and can be synchronized to DC (inhibit) for use in ultra low power burst mode power conversion.

Claims

1. An oscillator, comprising:

a voltage input terminal to receive an input voltage signal;

a synchronizing signal input terminal to receive a synchronizing signal;

a ramp timing resistance;

a ramp timing capacitor which is charged by the input voltage signal through the ramp timing resistance;

an input voltage resistor divider network coupled to the voltage input terminal and which produces a discharge trigger reference voltage that is proportional to a voltage of the input voltage signal;

a comparator that compares a voltage across the ramp timing capacitor to the discharge trigger reference voltage;

a logic circuit that in response to a first state of a synchronization signal, discharges the ramp timing capacitor and that in response to a second state of the synchronization signal when the value of the voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage, delays a discharging of the ramp timing capacitor, wherein at least the comparator and the logic circuit are each formed of a number of discrete semiconductor components;

a control transistor;

a discharge controlling capacitor;

a discharge termination transistor; and

a discharge controlling transistor, the control transistor responsive to at least an output of the comparator to selectively charge the discharge controlling capacitor from the voltage input terminal, the discharge controlling capacitor coupled to selectively cause the discharge controlling transistor and the discharge termination transistor to discharge the ramp timing capacitor.

2. The oscillator of claim 1 wherein the input voltage resistor divider network includes a first divider resistor and a second divider resistor, the input voltage resistor network coupled to provide the discharge trigger reference voltage to the comparator.

3. The oscillator of claim 2 wherein the input voltage resistor divider network further includes a temperature compensation resistor to compensate the discharge trigger reference voltage for temperature variation.

4. The oscillator of claim 2 wherein the comparator comprises a first comparator transistor and a second comparator transistor coupled as a differential pair of transistors, with a base of the first comparator transistor coupled as an inverting input to the input voltage resistor divider network to receive the discharge trigger reference voltage and a base of the second comparator transistor coupled as a non-inverting input to the ramp timing capacitor to receive the voltage across the ramp timing capacitor.

5. The oscillator of claim 1 wherein the comparator comprises a first comparator transistor and a second comparator transistor coupled as a differential pair of transistors.

6. The oscillator of claim 1 wherein the discharge controlling transistor selectively provides a path to a ground to at least approximately fully discharge the ramp timing capacitor to at least close to a zero voltage.

7. The oscillator of claim 6 wherein the logic circuit includes:

a synchronization capacitor coupled to the synchronization input terminal to receive the synchronization signal, a first diode coupled to cause the control transistor to be in a first state in response to a first state of the synchronization signal and a second diode coupled to the control transistor cause the control transistor to be in a second state in response to a second state of the synchronization signal.

8. The oscillator of claim 7, further comprising:

a level shifting diode electrically coupling a control transistor resistor to a ground to level shift the control transistor resistor reducing a voltage required to turn on the control transistor.

9. The oscillator of claim 1 wherein the ramp timing resistance comprises a first ramp resistor and a second ramp resistor electrically coupled in series with the first ramp resistor between the voltage input terminal and the ramp timing capacitor.

10. The oscillator of claim 1, further comprising:

a buffer transistor; and

a buffer resistor, the buffer transistor and the buffer resistor coupled to form an emitter follower buffer amplifier between a voltage supply and a ground to provide a low source impedance driver.

11. The oscillator of claim 1 wherein at least the ramp timing resistance and the ramp timing capacitor are formed as discrete components on a separate chip from the comparator and the logic circuit.

12. A method of operating an oscillator, the method comprising:

receiving an input voltage signal at a voltage input terminal;

receiving a synchronizing signal at a synchronizing signal input terminal;

charging a ramp timing capacitor via the input voltage signal through a ramp timing resistance;

producing a discharge trigger reference voltage that is proportional to a voltage of the input voltage signal;

comparing a voltage across the ramp timing capacitor to the discharge trigger reference voltage, wherein comparing the voltage across the ramp timing capacitor to the discharge trigger reference voltage includes supplying the discharge trigger reference voltage to a first transistor of a differential pair of transistors and supplying the voltage across the ramp timing capacitor to a second transistor of the differential pair of transistors;

determining whether to trigger discharging of the ramp timing capacitor when the value of the voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage, wherein determining whether to trigger discharging of the ramp timing capacitor when the value of the voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage includes supplying the synchronization signal to a logic network comprising a synchronization capacitor, a first synchronization diode and a second synchronization diode, triggering the discharging of the ramp timing capacitor via the first synchronization diode in response to a first synchronization state and suppressing triggering of the discharging of the ramp timing capacitor via the second synchronization diode in response to a second synchronization state;

in response to a value of the voltage across the ramp timing capacitor being equal to the discharge trigger reference voltage, discharging the ramp timing capacitor if a state of the synchronization signal indicates synchronization and delaying discharging of the ramp timing capacitor if the state of the synchronization signal does not indicate synchronization; and

in response to the state of the synchronization signal indicating synchronization while the voltage across the ramp timing capacitor is less than the discharge trigger reference voltage, discharging the ramp timing capacitor.

13. The method of claim 12, further comprising:

buffering an output voltage signal via a buffer amplifier.

14. The method of claim 13 wherein the buffering the output voltage signal via the buffer amplifier includes buffering the output voltage signal via an emitter follower buffer amplifier having a discrete transistor and resistor.

15. The method of claim 12 wherein the producing the discharge trigger reference voltage that is proportional to the voltage of the input voltage signal includes dividing the input voltage signal via an input voltage resistor divider network and temperature compensating the divided input voltage signal.