Microprocessor including a display interface in the microprocessor
First Claim
Patent Images
1. A processing system comprising:
- a first integrated circuit, wherein the first integrated circuit comprises a processor core, a display interface and memory controller coupled to a first bus interface; and
a second integrated circuit in communication with the first integrated circuit,wherein the second integrated circuit comprises a second bus interface for allowing communication with the first integrated circuit via the first bus interface and adapted to allow for communication to a graphics engine,wherein the processor core controls refresh operations when the graphics engine is powered off entirely, andwherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation.
3 Assignments
0 Petitions
Accused Products
Abstract
A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.
-
Citations
24 Claims
-
1. A processing system comprising:
-
a first integrated circuit, wherein the first integrated circuit comprises a processor core, a display interface and memory controller coupled to a first bus interface; and a second integrated circuit in communication with the first integrated circuit, wherein the second integrated circuit comprises a second bus interface for allowing communication with the first integrated circuit via the first bus interface and adapted to allow for communication to a graphics engine, wherein the processor core controls refresh operations when the graphics engine is powered off entirely, and wherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A method within a processing system;
- the processing system comprising a first integrated circuit and a second integrated circuit in communication therebetween;
the method comprising;providing a processor core, a display interface and a memory controller in the first integrated circuit, wherein the memory controller interfaces to a first memory; providing a graphics engine in the second integrated circuit;
wherein the graphics engine interfaces to a second memory;transferring graphics data from the second memory to the first memory via the display interface; and controlling refresh operations with the processor core when the graphics engine is powered off entirely, wherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation. - View Dependent Claims (13, 14, 15)
- the processing system comprising a first integrated circuit and a second integrated circuit in communication therebetween;
-
16. A processing system comprising:
-
a first integrated circuit, the first integrated circuit comprises a processor core and a CRT controller function; and a second integrated circuit in communication with the first integrated circuit, wherein the second integrated circuit includes a graphics engine, wherein the processor core controls refresh operations when the graphics engine is powered off entirely, and wherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation. - View Dependent Claims (17, 18, 19, 20, 21)
-
-
22. A processing system comprising:
-
a first integrated circuit, wherein the first integrated circuit comprises a processor core, a display interface and memory controller coupled to a first bus interface, wherein the first integrated circuit further comprises a CRT controller function, wherein the memory controller is coupled to a memory, via a first bus; and a second integrated circuit in communication with the first integrated circuit, wherein the second integrated circuit comprises a second bus coupled to the second bus interface; and
at least one I/O device coupled to the second bus,wherein the second integrated circuit further comprises a second bus interface for allowing communication with the first integrated circuit via the first bus interface and adapted to allow for communication to a graphics engine, wherein the graphics data is copied to the memory by the memory controller while the data is being sent by the graphics engine to the display interface, wherein the processor core is allowed to perform graphics operations when the graphics engine is powered off entirely, and wherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation. - View Dependent Claims (23)
-
-
24. A non-transitory computer readable medium that comprises a description of a processing system and where the system comprises:
-
a first integrated circuit, wherein the first integrated circuit comprises a processor core and a CRT controller function; and a second integrated circuit in communication with the first integrated circuit, wherein the second integrated circuit comprises a graphics engine, wherein the processor core controls refresh operations when the graphics engine is powered off entirely, and wherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation.
-
Specification