Microprocessor including a display interface in the microprocessor

• US 8,890,876 B1
• Filed: 12/21/2007
• Issued: 11/18/2014
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation), Sun Microsystems Technology Ltd. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Glaskowsky, Peter N.
• Primary Examiner(s): Merouan, Abderrahim
• Application Number:
  US11/963,603
• Time in Patent Office: 2,524 Days
• Field of Search: 345/156, 345/519, 345/501, 345/520, 345/503, 345/531, 710/5, 710/163, 710/313, 710/315, 710/312, 710/100, 710/306, 711/1, 711/103, 711/108, 711/115
• US Class Current: 345/519
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.

Claims

1. A processing system comprising:

a first integrated circuit, wherein the first integrated circuit comprises a processor core, a display interface and memory controller coupled to a first bus interface; and

a second integrated circuit in communication with the first integrated circuit,

wherein the second integrated circuit comprises a second bus interface for allowing communication with the first integrated circuit via the first bus interface and adapted to allow for communication to a graphics engine,

wherein the processor core controls refresh operations when the graphics engine is powered off entirely, and

wherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation.

2. The processing system of claim 1 wherein the second integrated circuit comprises:

at least one I/O device coupled to the second bus interface.

3. The processing system of claim 1 wherein the graphics engine is coupled to at least one from a group consisting of the second bus interface, a second display, and a second memory.

4. The processing system of claim 1, wherein the processor core controlling the refresh operations when the graphics is powered entirely off is done when the graphics processing is simple enough for the processor core which includes, but is not limited to, 2D-only functions, unchanging display content, idle periods between keystrokes, and when no applications are running.

5. The processing system of claim 1 wherein the graphics engine is internal to the second integrated circuit.

6. The processing system of claim 1 wherein the graphics engine is external to the second integrated circuit.

7. The processing system of claim 3, further comprising a third integrated circuit, wherein the third integrated circuit comprises a graphics engine that communicates with the first integrated circuit.

8. The processing system of claim 1 wherein the first integrated circuit further comprises a CRT controller function.

9. The processing system of claim 8, wherein the CRT controller function is within the display interface.

10. The processing system of claim 8, wherein the CRT controller function is capable of performing compositing operations.

11. The processing system of claim 3, wherein the processor core can perform the functions of the graphics engine and the graphics engine can be disabled.

12. A method within a processing system;

the processing system comprising a first integrated circuit and a second integrated circuit in communication therebetween;

the method comprising;

providing a processor core, a display interface and a memory controller in the first integrated circuit, wherein the memory controller interfaces to a first memory;

providing a graphics engine in the second integrated circuit;

wherein the graphics engine interfaces to a second memory;

transferring graphics data from the second memory to the first memory via the display interface; and

controlling refresh operations with the processor core when the graphics engine is powered off entirely,

wherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation.

13. The method of claim 12 wherein the graphics data is copied to the first memory by the memory controller while the data is being sent by the graphics engine to the display interface.

14. The method of claim 12 allowing the first integrated circuit to perform graphics operations when the second integrated circuit is powered off entirely.

15. The method of claim 12 wherein non-essential elements of the processing system are turned off during refresh operations.

16. A processing system comprising:

a first integrated circuit, the first integrated circuit comprises a processor core and a CRT controller function; and

a second integrated circuit in communication with the first integrated circuit,

wherein the second integrated circuit includes a graphics engine,

wherein the processor core controls refresh operations when the graphics engine is powered off entirely, and

wherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation.

17. The processing system of claim 16 wherein the CRT controller function is within a display interface in the first integrated circuit.

18. The processing system of claim 16 wherein the CRT controller function is capable of performing compositing operations.

19. The processing system of claim 16 wherein the first integrated circuit performs graphics operations when the second integrated circuit is powered off entirely.

20. The processing system of claim 16, further comprising a third integrated circuit, wherein the third integrated circuit comprises a graphics engine that communicates with the first integrated circuit.

21. The processing system of claim 16, wherein the processor core can perform the functions of the graphics engine and the graphics engine can be disabled.

22. A processing system comprising:

a first integrated circuit, wherein the first integrated circuit comprises a processor core, a display interface and memory controller coupled to a first bus interface,

wherein the first integrated circuit further comprises a CRT controller function, wherein the memory controller is coupled to a memory, via a first bus; and

a second integrated circuit in communication with the first integrated circuit,

wherein the second integrated circuit comprises a second bus coupled to the second bus interface; and

at least one I/O device coupled to the second bus,

wherein the second integrated circuit further comprises a second bus interface for allowing communication with the first integrated circuit via the first bus interface and adapted to allow for communication to a graphics engine, wherein the graphics data is copied to the memory by the memory controller while the data is being sent by the graphics engine to the display interface,

wherein the processor core is allowed to perform graphics operations when the graphics engine is powered off entirely, and

wherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation.

23. The processing system of claim 22 wherein the CRT controller function is capable of performing compositing operations.

24. A non-transitory computer readable medium that comprises a description of a processing system and where the system comprises:

a first integrated circuit, wherein the first integrated circuit comprises a processor core and a CRT controller function; and

a second integrated circuit in communication with the first integrated circuit,

wherein the second integrated circuit comprises a graphics engine,

wherein the processor core controls refresh operations when the graphics engine is powered off entirely, and

wherein whether the processor core controls refresh operations when the graphics is powered entirely off is determined based on whether a user will detect significant performance degradation.